Methods and systems of power management for an integrated circuit
AssigneeSemiconductor Components Industries, LLC
InventorIvo Leonardus Coenen
Life of this patent
Estimating the term…
Abstract
Power management for an integrated circuit. One example embodiment is a method of operating a portable audio device including: reading, by a supply controller, a logic speed measurement from a logic gate delay line, the supply controller and the logic gate delay line implemented on a semiconductor substrate; computing, by the supply controller, a speed margin based on the logic speed measurement; creating, by the supply controller, a value indicative of a modified voltage level, the creating based on the speed margin; and modifying, by a main voltage converter on the semiconductor substrate, an output voltage responsive to the value indicative of the modified voltage level.
Claims31
A method of operating an integrated circuit on a semiconductor substrate, the method comprising:
- reading, by a supply controller, a logic speed measurement from a logic gate delay line, the supply controller and the logic gate delay line implemented on a semiconductor substrate;
- computing, by the supply controller, a speed margin based on the logic speed measurement;
- creating, by the supply controller, a value indicative of a modified voltage, the creating based on the speed margin;
- and
- modifying, by a main voltage converter on the semiconductor substrate, an output voltage responsive to the value indicative of the modified voltage.
An integrated circuit on a semiconductor substrate, comprising:
- a processing core;
- a system memory coupled to the processing core;
- a main voltage converter that defines a main control input, a main supply input, and a main voltage output, the main voltage converter configured to vary a voltage driven to the main voltage output responsive to the main control input;
- a logic gate delay line embedded within the processing core, the logic gate delay line defines a plurality of gate outputs;
- and
- a supply controller that defines a plurality of gate inputs coupled to the plurality of gate outputs of the logic gate delay line, and a main control output coupled to the main control input of the main voltage converter, and the supply controller configured to:
- read the plurality of gate outputs from the logic gate delay line;
- create a logic speed measurement based on reading the plurality of gate outputs;
- compute a speed margin based on the logic speed measurement;
- and
- drive a value indicative of a modified voltage level to the main control output responsive to the speed margin.
An integrated circuit package, comprising:
- a first semiconductor die comprising:
- a processing core;
- a system memory coupled to the processing core;
- a bidirectional communication bus coupled to the processing core;
- a main voltage converter that defines a main control input, a main supply input, and a main voltage output, the main voltage converter configured to vary a voltage driven to the main voltage output responsive to the main control input;
- a logic gate delay line embedded within the processing core, the logic gate delay line defines a plurality of gate outputs;
- and
- a supply controller that defines a plurality of gate inputs coupled to the plurality of gate outputs of the logic gate delay line, and a main control output coupled to the main control input of the main voltage converter, and the supply controller configured to:
- read the plurality of gate outputs from the logic gate delay line;
- create a logic speed measurement based on reading the plurality of gate outputs;
- compute a speed margin based on the logic speed measurement;
- and
- drive a value indicative of a modified voltage level to the main control output responsive to the speed margin;
- a second semiconductor die comprising a wireless communication circuit coupled to the bidirectional communication bus, the wireless chip configured communicate wirelessly to devices outside the integrated circuit package;
- wherein the first semiconductor die and the second semiconductor die are co-packaged into the integrated circuit package.
Dependencies are inferred from the claim text.