Resistive memory device having a conductive barrier layer

A method of manufacturing a memory device, comprising:

• forming a bottom contact;
• connecting a memory layer to the bottom contact, wherein the memory layer comprises a memory layer material having a variable resistivity, and wherein the resistivity of the memory layer material is dependent on a concentration of ions or vacancies in the memory layer material;
• forming a top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, wherein the heterojunction memory structure is configured such that a memory state of the heterojunction memory structure is dependent on a controllably variable concentration of ions or vacancies in the memory layer material, and such that the memory state of the heterojunction memory structure is controllable by applying an electric field to control the concentration of ions or vacancies in the memory layer material;
• forming a top contact on the top electrode;
• forming a first barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the first barrier layer is between the top electrode and the top contact, and wherein the first barrier layer has a resistivity less than 1E-4 Ohm-m;
• and
• forming a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the second barrier layer is between the memory layer and the bottom contact, and wherein the first barrier layer has a resistivity less than 1E-4 Ohm-m.

A method of using a memory device, the memory device comprising:

• a bottom contact;
• a memory layer connected to the bottom contact, wherein the memory layer comprises a memory layer material having a variable resistivity, and wherein the resistivity of the memory layer material is dependent on a concentration of ions or vacancies in the memory layer material;
• a top electrode on the memory layer, wherein the top electrode and the memory layer cooperatively form a heterojunction memory structure, wherein the heterojunction memory structure is configured such that a memory state of the heterojunction memory structure is dependent on a controllably variable concentration of ions or vacancies in the memory layer material, and such that the memory state of the heterojunction memory structure is controllable by applying an electric field to control the concentration of ions or vacancies in the memory layer material;
• a top contact on the top electrode;
• a first barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the first barrier layer is between the top electrode and the top contact, and wherein the first barrier layer has a resistivity less than 1E-4 Ohm-m;
• and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, wherein the second barrier layer is between the memory layer and the bottom contact, and wherein the first barrier layer has a resistivity less than 1E-4 Ohm-m, the method comprising:
• applying a first voltage difference across the bottom contact and the top contact, whereby an electric field is generated in the memory layer, and such that a resistivity state of the memory layer is changed;
• applying a second voltage difference across the bottom contact and the top contact;
• while the second voltage difference is applied, causing a first current to be conducted through the bottom contact, the second barrier layer, the memory layer, the top electrode, the first barrier layer, and the top contact;
• and
• determining the resistivity state of the memory layer based on the second voltage and the first current.