Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts

A method for fabricating a semiconductor integrated circuit device, comprising:

• forming a metallization layer of a back-end-of-line structure, wherein the metallization layer comprises a first interlayer dielectric layer and a plurality of metallic structures formed in the first interlayer dielectric layer in a memory region and a non-memory region of the back-end-of line structure;
• forming a first insulation layer over the metallization layer, wherein the first insulation layer comprises a first bottom electrode via contact formed in the first insulation layer in the memory region;
• forming a second insulation layer over the first insulation layer, the second insulation layer comprising a second bottom electrode via contact formed in the second insulation layer in the memory region, wherein the second bottom electrode via contact is disposed over, and in contact with, the first bottom electrode via contact;
• forming a stack of layers over the second insulation layer, the stack of layers comprising (i) a bottom electrode layer formed over the second insulation layer, (ii) a magnetic tunnel junction layer stack formed over the bottom electrode layer, and (iii) an upper electrode layer formed over the magnetic tunnel junction layer stack;
• etching the stack of layers to form a memory device pillar comprising a bottom electrode, a magnetic tunnel junction structure, and an upper electrode, wherein the bottom electrode is disposed over, and in contact with, the second bottom electrode via contact, and wherein etching the stack of layers results in recessing an exposed portion of the second insulation layer;
• and
• depositing and etching a conformal layer of dielectric material to thereby form a dielectric spacer on sidewalls of the memory device pillar;
• wherein etching the conformal layer of dielectric material results in further recessing the exposed portion of the second insulation layer down to the first insulation layer, and partially recessing an exposed portion of the first insulation layer;
• wherein the partially recessed first insulation layer serves as a capping layer for the metallization layer;
• and
• forming a second interlayer dielectric layer to cover the partially recessed first insulation layer and the memory device pillar in the non-memory and memory regions of the back-end-of-line structure;
• and
• forming a plurality of metallic interconnect structures in the second interlayer dielectric layer, wherein the plurality of metallic interconnect structures comprise an upper electrode via contact which is formed in contact with the upper electrode of the memory device pillar in the memory region of the back-end-of-line structure.