Magnetoresistive random access memory device and method of manufacturing the same

A magnetoresistive random access memory (MRAM) device, comprising:

• a first insulating interlayer on a substrate, the first insulating interlayer containing a contact plug therein;
• a memory unit electrically connected to the contact plug, the memory unit including a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode that are sequentially stacked on the first insulating interlayer;
• a protective pattern structure on the first insulating interlayer, the protective pattern structure covering at least a sidewall of the memory unit and including a capping pattern, an insulation pattern and an etch stop pattern that are sequentially stacked, the capping pattern being monolithic and being directly on a lower electrode portion of the sidewall of the memory unit and an upper electrode portion of the sidewall of the memory unit;
• a second insulating interlayer on the protective pattern structure;
• and
• a wiring extending through the second insulating interlayer and the protective pattern structure, the wiring contacting a top surface of the upper electrode and physically contacting the capping pattern;
• wherein an uppermost surface of the insulation pattern is lower than the top surface of the upper electrode.

A magnetoresistive random access memory (MRAM) device, comprising:

• a memory unit on a substrate, the memory unit including a lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode that are sequentially stacked;
• a protective pattern structure on a sidewall of the memory unit, the protective pattern structure including a capping pattern, an insulating pattern, and an etch stop pattern that are sequentially stacked, the capping pattern being monolithic and being directly on a lower electrode portion of the sidewall of the memory unit and an upper electrode portion of the sidewall of the memory unit;
• and
• a wiring on the upper electrode,
• wherein a portion of the wiring is in physical contact with uppermost surfaces of the capping pattern, the insulating pattern, and the etch stop pattern;
• and
• wherein the uppermost surface of the insulating pattern is lower than an uppermost surface of the upper electrode.