Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

A nanowire device, comprising:

• a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire comprises:
• an undoped channel region of a first semiconductor material;
• an undoped semiconductor source region electrically coupled with a first end of the channel region;
• an undoped semiconductor drain region electrically coupled with a second end of the channel region;
• a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region;
• a source stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor source region and extending along at least a portion of the semiconductor source region;
• and
• a drain stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor drain region and extending along at least a portion of the semiconductor drain region;
• wherein the source stack comprises a source conductor contacting an interfacial layer disposed over the semiconductor source region, the interfacial layer including at least one epitaxial bilayer of group III and group V atomic monolayers.

A nanowire device, comprising:

• a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire comprises:
• an undoped channel region of a first semiconductor material;
• an undoped semiconductor source region electrically coupled with a first end of the channel region;
• an undoped semiconductor drain region electrically coupled with a second end of the channel region;
• a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region;
• a source stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor source region and extending along at least a portion of the semiconductor source region;
• and
• a drain stack electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor drain region and extending along at least a portion of the semiconductor drain region;
• wherein the source stack comprises a source conductor contacting the semiconductor source region and extending along at least a portion of the semiconductor source region, the source conductor comprising a degenerately p-type doped semiconductor and there is an offset in valence band energy between the degenerately doped p-type semiconductor and the semiconductor source region such that a valence band maximum in the degenerately doped p-type semiconductor is at a lower energy than a valence band maximum in the semiconductor source region.

A nanowire transistor, comprising:

• a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire comprises:
• an undoped channel region of a first semiconductor material;
• an undoped semiconductor source region electrically coupled with a first end of the channel region;
• an undoped semiconductor drain region electrically coupled with a second end of the channel region;
• a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region;
• a source stack comprising an interfacial layer and a source conductor, which is electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor source region and extending along at least a portion of the semiconductor source region;
• and
• a drain stack comprising an interfacial layer and a drain conductor, which is electrically isolated from the gate conductor, coaxially wrapping completely around the semiconductor drain region and extending along at least a portion of the semiconductor drain region;
• wherein a Schottky barrier between the source conductor and the semiconductor source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.