Confined source drain epitaxy to reduce shorts in CMOS integrated circuits

A method for increasing epitaxy to epitaxy spacing, the method comprising:

• depositing a first spin-on carbon (SOC) mask over an n-type field effect transistor (NFET) region of a semiconductor substrate;
• recessing a first set of fins in the p-type field effect transistor (PFET) region;
• growing first epitaxial source/drain regions over the PFET region such that a distal end of the first epitaxial source/drain regions defines a flattened surface resulting from contact with the first SOC mask;
• removing the first SOC mask;
• depositing a second SOC mask over PFET region of the semiconductor substrate;
• recessing a second set of fins in the NPFET region;
• growing second epitaxial source/drain regions over the NFET region such that a distal end of the second epitaxial source/drain regions defines a flattened surface resulting from contact with the second SOC mask;
• and
• removing the second SOC mask.