SOI wafers and devices with buried stressor
AssigneeAcorn Semi, LLC
InventorsPaul A. Clifton, Andreas Goebel
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
Claims5
An electrically isolated semiconductor device structure, including;
- a silicon substrate having first and second walls of two trench isolation structures extending partially into the substrate, the first and second walls defining a first lateral extent of a semiconductor device and a substrate interface region extending between the first and second walls;
- a buried stressor structure overlying the substrate interface region and extending over the first lateral extent between the first and second walls;
- a buried insulation structure overlying the buried stressor structure extending over the first lateral extent between the first and second walls and having an insulating upper region;
- a surface semiconductor layer formed on the buried insulation structure extending between the first and second walls and having uniaxial in-plane tensile strain induced over at least a portion of the surface semiconductor layer extending between the first and second walls, the strain induced by elastic edge relaxation of the stressor structure;
- the semiconductor device structure further having third and fourth walls of two trench isolation structures, the third and fourth walls orthogonal to the first and second walls and not extending into the silicon substrate, the third and fourth walls defining a second lateral extent of the device;
- the surface semiconductor layer formed on the buried insulation structure extending between the third and fourth walls.
Dependencies are inferred from the claim text.