Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate

A method of fabricating devices on a substrate, the method comprising:

• performing memory fabrication operations to form a non-volatile memory device in a first region of the substrate, wherein the memory fabrication operations include:
• forming a first region of the nanosheet stack over a first region of the substrate, wherein the first region of nanosheet stack comprises alternating layers of sacrificial nanosheets and non-sacrificial nanosheets;
• replacing at least a portion of the first region of the nanosheet stack with a control gate;
• and
• providing a charge trapping region of the non-volatile memory device under the control gate;
• performing nanosheet fabrication operations to form a nanosheet field effect transistor (FET) device in a second region of the substrate, wherein the nanosheet fabrication operations include:
• forming a second region of the nanosheet stack over a second region of the substrate, wherein the second region of the nanosheet stack comprises the alternating layers of sacrificial nanosheets and non-sacrificial nanosheets;
• forming bottom isolation regions over the second region;
• forming nanosheet source or drain (S/D) regions over the bottom isolation regions and adjacent end regions of the non-sacrificial nanosheets of the second region of the nanosheet stack;
• replacing the sacrificial nanosheets of the second region of the nanosheet stack with a first set of conductive gate regions;
• and
• forming a second conductive gate region over and around the second region of the nanosheet stack;
• and
• performing extended-gate (EG) fabrication operations to form an EG FET device in a third region of the substrate, wherein the EG fabrication operations include:
• forming a fin in the third region of the substrate;
• forming selected ones of the bottom isolation regions over the third region of the substrate and adjacent to a portion of the fin;
• forming EG S/D regions over the bottom isolation regions and adjacent sidewalls of the fin;
• and
• forming selected portions of the second conductive gate region over and around the fin.

An integrated circuit structure comprising:

• a first region of a nanosheet stack formed over a first region of a substrate, wherein the first region of the nanosheet stack comprises a nanosheet layer of a first type of semiconductor material and a nanosheet layer of a second type of semiconductor material;
• a control gate formed over the first region of the nanosheet stack of the non-volatile memory device;
• and
• a charge trapping region of the non-volatile memory device under the control gate, wherein the charge trapping region comprises the nanosheet layer of the first type of semiconductor material and the nanosheet layer of the second type of semiconductor material;
• memory source or drain (S/D) regions over the first region of the substrate;
• a portion of the first region of the substrate positioned between a first one of the S/D regions and a second one of the S/D regions;
• and
• a channel region comprising the portion of the first region of the substrate that is positioned between the first one of the S/D regions and the second one of the S/D regions;
• wherein a non-volatile memory device of the integrated circuit comprises a non-volatile memory transistor, the control gate, and the charge trapping region;
• and
• wherein the non-volatile memory transistor comprises:
• the first one of the S/D regions;
• the second one of the S/D regions;
• and
• the channel region.