Super long channel device within VFET architecture

A method for forming a semiconductor device, the method comprising:

• forming a pair of semiconductor fins on a substrate;
• forming a semiconductor pillar between the semiconductor fins on the substrate;
• forming a bottom doped region that extends under all of the semiconductor fins and under part of the semiconductor pillar;
• recessing the semiconductor pillar below a surface of the pair of semiconductor fins;
• forming a shared conductive gate over a channel region of the semiconductor fins and the semiconductor pillar, wherein a gate dielectric of the shared conductive gate is positioned on a first sidewall, a second sidewall, and a top surface of the semiconductor pillar;
• forming a thick oxide layer between the conductive gate and the semiconductor fins and the semiconductor pillar;
• forming a source region and a drain region on exposed surfaces of the semiconductor fins;
• and
• forming a shared gate contact on the conductive gate and over the semiconductor pillar;
• wherein a thickness of the semiconductor pillar is larger than a thickness of each of the pair of semiconductor fins;
• and
• wherein the pair of semiconductor fins and the semiconductor pillar are electrically coupled to define a single long channel transistor configured to pass a current through a first fin of the pair of semiconductor fins in a first direction and through a second fin of the pair of semiconductor fins in a second direction opposite the first direction.

A method of forming a semiconductor device, the method comprising:

• forming a first semiconductor fin and a second semiconductor fin on a substrate;
• forming a semiconductor pillar between the first semiconductor fin and the second semiconductor fin;
• forming a bottom doped layer that extends fully below the first semiconductor fin and the second semiconductor fin, but only partially below the semiconductor pillar;
• forming a shared gate over a sidewall of the first semiconductor fin, a sidewall of the second semiconductor fin, and a topmost surface of the semiconductor pillar, wherein a gate dielectric of the shared gate is positioned directly on a first sidewall, a second sidewall, and the topmost surface of the semiconductor pillar;
• and
• passing a current from a source region formed on a top surface of the first semiconductor fin to a drain region formed on a top surface of the second semiconductor fin through the semiconductor pillar, wherein the current passes from a first portion of the bottom doped layer that extends below a first sidewall of the semiconductor pillar to the topmost surface of the semiconductor pillar.