Semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorKeiji Okumura
Life of this patent
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AssigneeFuji Electric Co., Ltd.
InventorKeiji Okumura
Estimating the term…
In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad.
A semiconductor device comprising:
Dependencies are inferred from the claim text.