Manufacturing method of semiconductor device and semiconductor device

A manufacturing method of a semiconductor device comprising the steps of:

• (a) preparing a substrate provided with an SiC layer including a drift layer, a channel layer on the drift layer, and a source region on the channel layer;
• (b) sequentially forming a stopper film and a first semiconductor region on the SiC layer;
• (c) forming a trench in a first insulating film disposed on the SiC layer, the stopper film, and the SiC layer, the trench penetrating the first insulating film, the stopper film, the source region, and the channel layer to reach the drift layer;
• (d) embedding a dummy gate in the trench;
• (e) removing the first insulating film such that the dummy gate protrudes from the stopper film;
• (f) forming side wall films on side walls of the dummy gate;
• (g) ion-implanting impurities of a conductivity type opposite to that of the drift layer with using the dummy gate and the side wall films as a mask, thereby forming the first semiconductor region in the drift layer on one side of the trench and forming a second semiconductor region in the drift layer on the other side of the trench;
• (h) removing the dummy gate, the stopper film, and the side wall films;
• (i) forming a gate insulating film on an inner wall of the trench;
• and
• (j) forming a gate electrode on the gate insulating film, the gate electrode being embedded in the trench,
• wherein the first semiconductor region and the second semiconductor region are located at a separate from a lower surface of the channel layer.

A semiconductor device comprising:

• an SiC layer including a drift layer, a channel layer on the drift layer, and a source region on the channel layer;
• a trench penetrating the channel layer to reach the drift layer and contacting with the source region;
• a gate insulating film formed on an inner wall of the trench;
• a gate electrode embedded in the trench;
• and
• a first semiconductor region formed in the drift layer on one side of the trench and a second semiconductor region formed in the drift layer on the other side of the trench,
• wherein the first semiconductor region and the second semiconductor region are located at a separate from a lower surface of the channel layer, and
• wherein a portion of the first semiconductor region and a portion of the second semiconductor region overlaps an upper portion of the gate electrode in a plan view.