Low resistance contact interlayer for semiconductor devices

A semiconductor device, comprising:

• a substrate;
• a p-doped channel layer including a doped III-V material on the substrate;
• a gate structure on the p-doped channel layer including a gate conductor and sidewall spacers;
• an n-type ZnO material formed directly on or in the p-doped channel layer adjacent to, and extending below, the gate structure, with a top surface of the n-type ZnO material and a top surface of the gate structure forming a co-planar surface, wherein the n-type ZnO material forms a source/drain region of the semiconductor device;
• an oxygen scavenging interlayer formed directly on the top surface of the n-type ZnO material to absorb oxygen from the n-type ZnO material, the oxygen scavenging interlayer including one of Ti and Er and having a thickness of about 10 nm or less;
• and
• an aluminum contact formed in direct contact with the oxygen scavenging interlayer to form an electronic device, the thickness of the oxygen scavenging layer providing a contact resistivity of less than about 2.0×10−8 Ohm-cm2.

A method for forming a semiconductor device, comprising:

• forming a p-doped channel layer including a doped III-V material on a substrate;
• forming a gate structure on the p-doped channel layer including a gate conductor and sidewall spacers;
• forming a source/drain region of the semiconductor device with an n-type doped II-VI material directly on or in the p-doped channel layer adjacent to, and extending below, the gate structure, with a top surface of the n-type doped II-VI material and a top surface of the gate structure forming a co-planar surface;
• forming an oxygen scavenging interlayer directly on the top surface of the n-type doped II-VI material to absorb oxygen from the n-type doped II-VI material;
• and
• forming a contact on the oxygen scavenging interlayer, the oxygen scavenging layer having a thickness providing a contact resistivity of less than about 2.0×10−8 Ohm-cm2.