Low-resistance top contact on VTFET
AssigneeInternational Business Machines Corporation
InventorsChristopher J. Waskiewicz, Su Chen Fan, Hari Prasad Amanapu, Hemanth Jagannathan
Life of this patent
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Abstract
A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.
Claims8
A method of forming a semiconductor device, the method comprising:
- forming a vertical semiconductor fin including a bottom end that contacts a semiconductor substrate;
- forming a top source/drain region on a top end of the vertical semiconductor fin and on sidewalls of the vertical semiconductor fin, the top source/drain region separated from the semiconductor substrate by the vertical semiconductor fin;
- forming an electrically conductive cap on an outer surface of the top source/drain region;
- forming a first dielectric trench liner adjacent a first side of the electrically conductive cap and forming a second dielectric liner adjacent a second side of the electrically conductive cap opposite the first side;
- and
- forming an electrically conductive contact via between the first and second dielectric liners and in ohmic connection with the electrically conductive cap.
Dependencies are inferred from the claim text.