US 10,833,172 B2 · Gate stack reliability in vertical transport field effect transistors

Abstract

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.

Claims20

Dependent claims

A method for forming a semiconductor structure, the method comprising at least:

forming at least one semiconductor fin;
forming a source/drain layer in contact with the semiconductor fin;
forming an interfacial layer in contact with sidewalls of the semiconductor fin and above the source/drain layer;
forming an insulating layer in contact with the interfacial layer;
and
encapsulating the interfacial layer and the insulating layer with one or more conductive gate layers.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/104,230Filed 17 Aug 2018

Published

US 2020/0058766 A120 Feb 2020

Granted

10 Nov 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification27 codes

H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10D 30/63
Insulated-gate field-effect transistors [IGFET]: vertical IGFETs
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Gate stack reliability in vertical transport field effect transistors

Life of this patent

Gate stack reliability in vertical transport field effect transistors

Life of this patent

Abstract

Claims20