Low-k gate spacer and methods for forming the same

A method of forming a semiconductor device, the method comprising:

• forming a first fin structure in a first substrate region;
• forming a second fin structure in a second substrate region;
• forming a first dummy gate stack over the first fin structure;
• forming a second dummy gate stack over the second fin structure;
• forming a first gate spacer layer over the first fin structure, the first dummy gate stack, the second fin structure, and the second dummy gate stack;
• forming a first sacrificial layer over the first gate spacer layer in the first substrate region and the second substrate region;
• forming a first mask over the first sacrificial layer in the second substrate region;
• performing a first etch process to remove portions of the first sacrificial layer and the first gate spacer layer and to expose portions of the first fin structure, wherein after performing the first etch process remaining portions of the first gate spacer layer adjacent the first dummy gate stack form a first gate spacer, wherein after performing the first etch process portions of sidewalls of the first dummy gate stack remain covered by the first sacrificial layer and the first gate spacer;
• growing first source/drain region on the first fin structure;
• removing the first mask;
• removing remaining portions of the first sacrificial layer;
• forming a second sacrificial layer over the first gate spacer layer in the second substrate region and over the first gate spacer in the first substrate region;
• forming a second mask over the second sacrificial layer in the first substrate region;
• performing a second etch process to remove portions of the second sacrificial layer and the first gate spacer layer in the second substrate region, wherein after performing the second etch process remaining portions of the first gate spacer layer adjacent the second dummy gate stack form a second gate spacer, remaining portions of the first gate spacer layer adjacent the second fin structure form spacer portions on opposing sides of the second fin structure, wherein after performing the second etch process portions of sidewalls of the second dummy gate stack remain covered by the second sacrificial layer and the second gate spacer;
• growing second source/drain region on the second fin structure, wherein the second source/drain region is adjacent the second gate spacer;
• removing remaining portions of the second sacrificial layer;
• and
• forming a second gate spacer layer over the first gate spacer in the first substrate region and over the second gate spacer layer in the second substrate region.

A semiconductor device comprising:

• a first transistor on a substrate, the first transistor comprising:
• a first epitaxial source/drain region over a first fin;
• a first metal gate structure adjacent the first epitaxial source/drain region, wherein the first metal gate structure includes:
• a first high-k dielectric layer over the first fin;
• and
• a first gate electrode over the first high-k dielectric layer;
• a first gate spacer along a sidewall of the first metal gate structure;
• and
• a second gate spacer along a sidewall of the first gate spacer and over the first epitaxial source/drain region, wherein the first gate spacer is disposed between the first metal gate structure and the second gate spacer, wherein a thickness of the second gate spacer is 40% to 70 % of a total thickness of the first gate spacer and the second gate spacer;
• and
• a second transistor on the substrate, the second transistor comprising:
• a second epitaxial source/drain region over a second fin, the second epitaxial source/drain region having a smaller cross-sectional area than the first epitaxial source/drain region;
• a second metal gate structure adjacent the second epitaxial source/drain region, wherein the second metal gate structure includes:
• a second high-k dielectric layer over the second fin;
• and
• a second gate electrode over the second high-k dielectric layer;
• a third gate spacer along a sidewall of the second metal gate structure;
• a fourth gate spacer along a sidewall of the second gate spacer and over the second epitaxial source/drain region, wherein the third gate spacer is disposed between the second metal gate structure and the fourth gate spacer;
• and
• spacer portions along opposing sidewalls of the second epitaxial source/drain region.