US 10,833,161 B2Granted

Semiconductor device and method

AssigneesImec Vzw, Globalfoundries Inc.

InventorsSyed Muhammad Yasser Sherazi, Julien Ryckaert, Juergen Boemmels, Guillaume Bouche

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

Claims20

Dependent claims

A method comprising:

forming, in an insulating layer, a first set of source/drain contact openings, wherein the insulating layer covers:
(i) a first elongated semiconductor structure extending in a first horizontal direction along a substrate and protruding vertically above the substrate, and (ii) a second elongated semiconductor structure extending along the substrate in parallel with the first semiconductor structure and protruding vertically above the substrate, wherein the first set of source/drain contact openings are formed above a first set of regions of an upper portion of the first semiconductor structure,
wherein forming the first set of source/drain contact openings comprises forming a first source/drain contact opening above a first region of the first set of regions of the first semiconductor structure, wherein the first source/drain contact opening includes:
(i) a first deep portion formed directly above the first region of the first semiconductor structure, and (ii) a first shallow portion formed adjacent to the first deep portion and extending vertically through the insulating layer, such that a level of a bottom surface of the first shallow portion is located above a level of a directly opposite first region of an upper portion of the second semiconductor structure, wherein the first shallow portion protrudes from the first deep portion in a second horizontal direction towards the first region of the second semiconductor structure and to a horizontal position disposed at least halfway between the first semiconductor structure and the second semiconductor structure;
wherein forming the first source/drain contact opening comprises:
forming the first deep portion by etching the insulating layer above the first region of the first semiconductor structure,
filling, at least partially, the first deep portion with a fill material,
forming the first shallow portion by etching the insulating layer selectively to the fill material adjacent to the first deep portion, and
removing the fill material in the first deep portion by etching the fill material selectively to the insulating layer;
forming a first set of source/drain contacts in the first set of source/drain contact openings, wherein forming the first set of source/drain contacts comprises forming a first source/drain contact in the first source/drain contact opening, wherein the first source/drain contact includes:
(i) a first vertically extending contact portion arranged in the first deep portion and (ii) a first via landing portion arranged in the first shallow portion and protruding horizontally from the first vertically extending contact portion;
and
forming an interconnection level, the interconnection level including a first vertical via abutting the first via landing portion.

10 more elements

A method comprising:

forming, in an insulating layer, a first set of source/drain contact openings, wherein the insulating layer covers:
(i) a first elongated semiconductor structure extending in a first horizontal direction along a substrate and protruding vertically above the substrate, and (ii) a second elongated semiconductor structure extending along the substrate in parallel with the first semiconductor structure and protruding vertically above the substrate, wherein the first set of source/drain contact openings are formed above a first set of regions of an upper portion of the first semiconductor structure,
wherein forming the first set of source/drain contact openings comprises forming a first source/drain contact opening above a first region of the first set of regions of the first semiconductor structure, wherein the first source/drain contact opening includes:
(i) a first deep portion formed directly above the first region of the first semiconductor structure, and (ii) a first shallow portion formed adjacent to the first deep portion and extending vertically through the insulating layer, such that a level of a bottom surface of the first shallow portion is located above a level of a directly opposite first region of an upper portion of the second semiconductor structure, wherein the first shallow portion protrudes from the first deep portion in a second horizontal direction towards the first region of the second semiconductor structure and to a horizontal position disposed at least halfway between the first semiconductor structure and the second semiconductor structure;
wherein forming the first source/drain contact opening comprises:
forming, on the insulating layer, a first contact etch mask that includes a first opening above the first region of the first semiconductor structure,
forming the first deep portion by etching the insulating layer through the first opening,
depositing a fill material layer covering the first contact etch mask and filling the first deep portion,
forming, on the fill material layer, a second contact etch mask that includes a second opening above a region of the insulating layer adjacent to the first deep portion,
etching the fill material layer through the second opening, such that (i) a portion of the first contact etch mask formed above the region of the insulating layer adjacent to the first deep portion is exposed and (ii) a portion of the fill material layer remains in the first deep portion,
removing the portion of the first contact etch mask to expose the region of the insulating layer adjacent to the first deep portion, thereby fixating an enlarged opening in the first contact etch mask,
forming the first shallow portion by etching the insulating layer through the enlarged opening selectively to the fill material layer portion, and
removing the fill material in the first deep portion by etching the fill material selectively to the insulating layer;
forming a first set of source/drain contacts in the first set of source/drain contact openings, wherein forming the first set of source/drain contacts comprises forming a first source/drain contact in the first source/drain contact opening, wherein the first source/drain contact includes:
(i) a first vertically extending contact portion arranged in the first deep portion and (ii) a first via landing portion arranged in the first shallow portion and protruding horizontally from the first vertically extending contact portion;
and
forming an interconnection level, the interconnection level including a first vertical via abutting the first via landing portion.

14 more elements

A method comprising:

forming, in an insulating layer, a first set of source/drain contact openings, wherein the insulating layer covers:
(i) a first elongated semiconductor structure extending in a first horizontal direction along a substrate and protruding vertically above the substrate, and (ii) a second elongated semiconductor structure extending along the substrate in parallel with the first semiconductor structure and protruding vertically above the substrate, wherein the first set of source/drain contact openings are formed above a first set of regions of an upper portion of the first semiconductor structure,
wherein forming the first set of source/drain contact openings comprises forming a first source/drain contact opening above a first region of the first set of regions of the first semiconductor structure, wherein the first source/drain contact opening includes:
(i) a first deep portion formed directly above the first region of the first semiconductor structure, and (ii) a first shallow portion formed adjacent to the first deep portion and extending vertically through the insulating layer, such that a level of a bottom surface of the first shallow portion is located above a level of a directly opposite first region of an upper portion of the second semiconductor structure, wherein the first shallow portion protrudes from the first deep portion in a second horizontal direction towards the first region of the second semiconductor structure and to a horizontal position disposed at least halfway between the first semiconductor structure and the second semiconductor structure;
forming a first set of source/drain contacts in the first set of source/dram contact openings, wherein forming the first set of source/drain contacts comprises forming a first source/drain contact in the first source/drain contact opening, wherein the first source/drain contact includes:
(i) a first vertically extending contact portion arranged in the first deep portion and (ii) a first via landing portion arranged in the first shallow portion and protruding horizontally from the first vertically extending contact portion;
forming, in the insulating layer, a second set of source/strain contact openings above a second set of regions of the upper portion of the second semiconductor structure;
subsequent to forming the second set of source/drain contact openings, forming a contact spacer layer on one or more sidewalls of the second set of source/drain contact openings;
subsequent to forming the contact spacer layer, forming a second set of source/drain contacts in the second set of source/drain contact openings;
and
forming an interconnection level, the interconnection level including a first vertical via abutting the first via landing portion.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/253,321Filed 22 Jan 2019
Priority: EP 1815277922 Jan 2018
Published: US 2019/0229196 A125 Jul 2019
Granted: 10 Nov 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6211
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
H10D 62/151
Source or drain regions of field-effect devices: of igfets