Field-effect transistors with self-aligned and non-self-aligned contact openings

A method comprising:

• forming a first section of an interlayer dielectric layer over a first source/drain region of a first field-effect transistor;
• forming a second section of the interlayer dielectric layer over a second source/drain region of a second field-effect transistor;
• forming a first sacrificial layer over the first section and the second section of the interlayer dielectric layer;
• forming a second sacrificial layer over the first sacrificial layer;
• forming a first mandrel and a second mandrel on the second sacrificial layer, wherein the second mandrel is separated from the first mandrel by a gap that is arranged over the first section of the interlayer dielectric layer;
• forming a first sidewall spacer on the first mandrel and a second sidewall spacer on the second mandrel that narrow the gap;
• transferring a first pattern that includes the first mandrel, the second mandrel, the first sidewall spacer, and the second sidewall spacer to the second sacrificial layer with a first etching process such that the second sacrificial layer includes a first opening over the first section of the interlayer dielectric layer at a location of the gap;
• removing the first mandrel, the second mandrel, the first sidewall spacer, and the second sidewall spacer following the first etching process;
• transferring the first pattern from the second sacrificial layer to the first sacrificial layer with a second etching process such that the first sacrificial layer includes a second opening over the first section of the interlayer dielectric layer at a location of the first opening;
• etching the first section and the second section of the interlayer dielectric layer with a third etching process that transfers the first pattern from the first sacrificial layer to the first section of the interlayer dielectric layer and that fully removes the second section of the interlayer dielectric layer, wherein a third opening is formed in the first section of the interlayer dielectric layer at a location of the second opening in the first sacrificial layer;
• before forming the first mandrel and the second mandrel, patterning the second sacrificial layer with a fourth etching process to form a second pattern including a section of the second sacrificial layer and a trench arranged over a third section of the interlayer dielectric layer;
• and
• depositing a layer of image reversal material in the trench to form a third pattern that is complementary to the second pattern.