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US 10,833,155 B2Granted
Vertical field effect transistor with top and bottom airgap spacers
AssigneeInternational Business Machines Corporation
InventorsChun-Chen Yeh, Veeraraghavan S. Basker, Junli Wang, Alexander Reznicek
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Abstract
A vertical field effect transistor (VFET) having a bottom airgap spacer located beneath a gate structure and a top airgap spacer located above the gate structure is provided. The top airgap spacer reduces overlap capacitance between the gate structure and a top source/drain structure of the VFET, while the bottom airgap spacer reduces the overlap capacitance and a coupling capacitance that is present between the gate structure and a bottom source/drain structure of the VFET.
Claims11
A semiconductor structure comprising:
- at least one vertical semiconductor material structure having a bottommost surface contacting a surface of a bottom source/drain structure and a topmost surface contacting a surface of a top source/drain structure;
- a gate structure located laterally adjacent to a sidewall of the at least one vertical semiconductor material structure;
- a bottom airgap spacer located between the gate structure and the bottom source/drain structure and contacting a lower portion of the sidewall of the at least one vertical semiconductor material structure;
- and
- a top airgap spacer located above the gate structure and contacting an upper portion of the sidewall of the at least one vertical semiconductor material structure, wherein the bottom airgap spacer and the top airgap spacer have a lateral width that is equal to a lateral width of the gate structure.
2 more elements
A semiconductor structure comprising:
- at least one vertical semiconductor material structure having a bottommost surface contacting a surface of a bottom source/drain structure and a topmost surface contacting a surface of a top source/drain structure;
- a gate structure located laterally adjacent to a sidewall of the at least one vertical semiconductor material structure;
- a bottom airgap spacer located between the gate structure and the bottom source/drain structure and contacting a lower portion of the sidewall of the at least one vertical semiconductor material structure;
- a top airgap spacer located above the gate structure and contacting an upper portion of the sidewall of the at least one vertical semiconductor material structure a lower interlayer dielectric material layer located laterally adjacent the least one vertical semiconductor material structure
- an upper interlayer dielectric material layer located on the lower interlayer dielectric material layer, and embedding an upper portion of the top source/drain structure;
- and
- a bottom contact structure extending through both the upper and lower interlayer dielectric material layers and contacting the bottom source/drain structure, and a top contact structure extending through the upper nterlayer dielectric material layer and contacting the top source/drain structure.
4 more elements
Dependencies are inferred from the claim text.