Three dimensional stacked semiconductor memory device

A semiconductor memory device comprising:

• a word line extended in a first horizontal direction;
• a bit line stack extended in a second horizontal direction perpendicular to the first horizontal direction;
• and
• a cell pillar extended from the word line to vertically pass through the bit line stack,
• wherein a first end of the cell pillar is electrically coupled to the word line, and
• a second end of the cell pillar is floated,
• wherein the bit line stack comprises a plurality of bit lines which are stacked in a vertical direction and are extended in parallel to each other in the second horizontal direction,
• wherein the second end of the cell pillar protrudes from a lowermost end of the bit line stack, and
• wherein the second end of the cell pillar is not coupled to other conductive components.

A semiconductor memory device comprising:

• a substrate;
• a lower insulating layer disposed over the substrate;
• a plurality of bit lines and a plurality of interlayer dielectric layers which are alternately stacked over the lower insulating layer, wherein the plurality of bit lines are extended in parallel to each other in a first horizontal direction;
• an upper insulating layer disposed over the plurality of bit lines;
• a word line disposed over the upper insulating layer and extended in a second horizontal direction perpendicular to the first horizontal direction;
• and
• a vertical pillar extended vertically from the word line through the upper insulating layer, the plurality of interlayer dielectric layers, and the plurality of bit lines,
• wherein the vertical pillar comprises a conductive core and at least three variable resistance layers surrounding the core,
• an upper end of the vertical pillar is directly connected to the word line;
• and
• a lower end of the vertical pillar protrudes into the lower insulating layer not to contact the substrate.