Solid-state imaging apparatus
AssigneeCanon Kabushiki Kaisha
InventorsYusuke Onuki, Masahiro Kobayashi, Takafumi Miki
Life of this patent
Estimating the term…
Abstract
An inventive solid-state imaging apparatus is provided which can improve the efficiency of the electric carrier transfer from a photoelectric conversion portion to an electric-carrier accumulation portion. The solid-state imaging apparatus includes an active region having the photoelectric conversion portion, the electric-carrier accumulation portion, and a floating diffusion, and an element isolation region having an insulator defining the active region. In planer view, the width of the active region in the electric-carrier accumulation portion under a gate of the first transfer transistor is larger than the width of the active region in the photoelectric conversion portion under the gate of the first transfer transistor.
Claims13
A photoelectric conversion apparatus in which a plurality of pixels are laid out in a matrix form, each of the pixels having an imaging region having a photoelectric conversion portion, a first transfer transistor configured to transfer electric carriers from the photoelectric conversion portion, an electric-carrier accumulation portion to which the electric carriers are transferred from the first transfer transistor, a second transfer transistor configured to transfer electric carriers accumulated in the electric-carrier accumulation portion, and a floating diffusion to which the electric carriers are transferred from the second transfer transistor, the solid-state imaging apparatus comprising:
- an active region having the photoelectric conversion portion, the electric-carrier accumulation portion, and the floating diffusion;
- and
- an element isolation region having an insulator defining the active region;
- wherein, in a predetermined direction in plan view, a first total length from a first boundary where the element isolation region contacts the active region to a second boundary where the element isolation region contacts the active region in the electric-carrier accumulation portion under a gate of the first transfer transistor is larger than a second total length from a third boundary where the element isolation region contacts the active region to a fourth boundary where the element isolation region contacts the active region in the photoelectric conversion portion under the gate of the first transfer transistor, and
- wherein, in the predetermined direction in plan view, the active region having the photoelectric conversion portion has a third total length from a fifth boundary where the element isolation region contacts the active region to a sixth boundary where the element isolation region contacts the active region that is larger than the second total length.
A photoelectric conversion apparatus comprising:
- a photoelectric conversion portion having a first semiconductor region of a first conductivity type;
- a first transfer transistor configured to transfer electric carriers from the photoelectric conversion portion;
- an electric-carrier accumulation portion having a second semiconductor region of the first conductivity type, the electric-carrier accumulating portion receiving the electric carriers transferred from the first transfer transistor;
- a second transfer transistor configured to transfer electric carriers accumulated in the electric-carrier accumulation portion;
- a floating diffusion to which the electric carriers are transferred from the second transfer transistor;
- wherein, at a side where the photoelectric conversion portion is provided, the first semiconductor region is placed between a third semiconductor region of a second conductivity type which is different from the first conductivity type and a fourth semiconductor region of the second conductivity type in a cross section in a channel width direction of the first transfer transistor under the gate of the first transfer transistor,
- wherein, at a side where the electric-carrier accumulation portion is provided, the second semiconductor region is placed between a fifth semiconductor region of the second conductivity type and a sixth semiconductor region of the second conductivity type in a cross section in the channel width direction of the first transfer transistor under the gate of the first transfer transistor,
- wherein a first total length of a first line from a first boundary where the second semiconductor region contacts the fifth semiconductor region to a second boundary where the second semiconductor region contacts the sixth semiconductor region is larger than a second total length of a second line from a third boundary where the first semiconductor region contacts the third semiconductor region to a fourth boundary where the first semiconductor region contacts the fourth semiconductor region in a cross section in the channel width direction of the first transfer transistor and
- wherein, in the channel width direction of the first transfer transistor in plan view, the first semiconductor region has a third total length of a third line from a fifth boundary where the first semiconductor region contacts the third semiconductor region to a sixth boundary where the first semiconductor region contacts the fourth semiconductor region that is larger than the second total length,
- wherein, the first boundary, the second boundary, the third boundary, and the fourth boundary are located under the gate of the first transfer transistor, and
- wherein the first line is parallel to the second line, and the second line is parallel to the third line.
Dependencies are inferred from the claim text.