Low power 2D memory transistor for flexible electronics and the fabrication methods thereof
AssigneeMitsubishi Electric Research Laboratories, Inc.
InventorsKoon Hoo Teo, Pin-Chun Shen, Chungwei Lin
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Abstract
Devices and methods of a transistor device that include a flexible memory cell. The flexible memory cell having a gate stack with sidewalls provided over a substrate. The gate stack including a metal gate layer provided over the substrate. A buffer layer provided over the metal gate layer. A ferroelectric layer provided over the buffer layer. A dielectric layer provided over the ferroelectric layer. Further, a two-dimensional (2D) material layer provided over a portion of a top surface of the dielectric layer. Source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity that the 2D material layer are located.
Claims28
A transistor device including a memory cell, the memory cell comprising:
- a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
- a metal gate layer provided over the supporting substrate;
- a titanium nitride (TiN) buffer layer provided between the metal gate layer and a ferroelectric layer;
- and
- a dielectric layer provided over the ferroelectric layer;
- a two-dimensional (2D) material layer provided onto a portion of a top surface of the dielectric layer;
- and
- source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity in which the 2D material layer is positioned in the cavity.
A transistor device having a resistive switching memory cell, the resistive switching memory cell comprising:
- a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
- a metal gate layer provided over the supporting substrate;
- a titanium nitride (TiN) buffer layer provided between the metal gate layer and a ferroelectric layer;
- and
- a dielectric layer provided over the ferroelectric layer;
- two-dimensional (2D) materials that are a MoS2 monolayer including grown MoS2 flakes transferred onto a portion of a top surface of the dielectric layer;
- and
- source and drain regions provided on separate portions of the top surface of the dielectric layer which create a cavity in which the 2D material layer is positioned in the cavity.
A single-layer molybdenum disulfide (MoS2) ferroelectric field-effect transistor (FeFET) including a memory cell, the memory cell comprising:
- a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
- a metal layer acting as a metal gate provided over a supporting substrate;
- a titanium nitride (TiN) buffer layer provided between the metal layer and an inorganic ferroelectric film of zirconium-doped hafnium oxide (HfZrOx);
- a dielectric hafnium(IV) oxide (HfO2) layer provided over the HfZrOx film;
- a two-dimensional (2D) material layer including grown MoS2 flakes transferred on to a portion of a top surface of the HfO2 layer;
- and
- source and drain regions provided on separate portions on the top surface of the HfO2 layer so as to create a cavity in which the 2D material layer is positioned in the cavity.
A transistor device including a memory cell, the memory cell comprising:
- a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
- a metal gate layer is a titanium (Ti)/gold (Au) acting as a gate electrode provided over the supporting substrate;
- a titanium nitride (TiN) buffer layer provided between the metal gate layer and a ferroelectric layer;
- and
- a dielectric layer provided over the ferroelectric layer, wherein the ferroelectric layer is an inorganic ferroelectric film of zirconium-doped hafnium oxide (HfZrOx) layer, and the dielectric layer is a dielectric hafnium (IV) oxide (HfO2) layer acting as a passivation layer;
- a two-dimensional (2D) material layer provided onto a portion of a top surface of the dielectric layer;
- and
- source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity in which the 2D material layer is positioned in the cavity.
A transistor device including a memory cell, the memory cell comprising:
- a gate stack with sidewalls provided over a supporting substrate, the gate stack including:
- a metal gate layer is a titanium (Ti)/gold (Au) acting as a gate electrode provided over the supporting substrate;
- a titanium nitride (TiN) buffer layer provided between the metal gate layer and a ferroelectric layer;
- and
- a dielectric layer provided over the ferroelectric layer, wherein a ratio of thicknesses between dielectric layer and the ferroelectric layer is about 0.3 to 0.5, so as to reduce an amount of switching voltage;
- a two-dimensional (2D) material layer provided onto a portion of a top surface of the dielectric layer;
- and
- source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity in which the 2D material layer is positioned in the cavity.
Dependencies are inferred from the claim text.