Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array
AssigneeMagnaChip Semiconductor, Ltd.
InventorsSu Jin Kim, Hye Jin Yoo
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Abstract
A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
Claims16
A single poly non-volatile memory device array, comprising:
- a cell comprising a source electrode, a gate of a selection transistor, a drain region of the selection transistor, a gate of a sensing transistor, a source region of the sensing transistor, and a drain electrode sequentially formed on a first well, and
- a control gate formed on a second well,
- wherein the control gate on the second well is connected to the gate of the sensing transistor on the first well, and
- wherein the drain region of the selection transistor shares the source region of the sensing transistor.
A single poly non-volatile memory device, comprising:
- a first type lower well;
- first and second wells disposed in the first type lower well and separated from each other;
- a source electrode, a gate of a selection transistor, a gate of a sensing transistor, and a drain electrode sequentially disposed on the first well;
- and
- a control gate formed on the second well and connected to the gate of the sensing transistor,
- wherein program and erase operation voltages are applied to the control gate and the source electrode, respectively.
Dependencies are inferred from the claim text.