Integrated circuit and method of manufacturing the same

A method, comprising the steps of:

• depositing a first polysilicon layer;
• etching the first polysilicon layer to form a first capacitor electrode and a transistor gate;
• depositing, in order, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on both the first capacitor electrode and transistor gate;
• depositing a second polysilicon layer;
• etching the second polysilicon layer to form a second capacitor electrode separated from the first capacitor electrode by the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer;
• etching a portion of the second silicon oxide layer that is not covered by the second capacitor electrode to leave first portions of the first silicon oxide layer and the silicon nitride layer extending beyond side edges of the second capacitor electrode;
• forming first sidewall spacers on the side edges of the second capacitor electrode, adjacent a side edge of the first capacitor electrode and adjacent side edges of the transistor gate, wherein said first sidewall spacers rest on the first portions of the silicon nitride layer;
• etching a portion of the silicon nitride layer that is not covered by the first sidewall spacers to leave second portions of the first silicon oxide layer;
• and
• forming second sidewall spacers adjacent said side edge of the first capacitor electrode and adjacent side edges of the second capacitor electrode and the transistor gate, wherein said second sidewall spacers rest on the second portions of the first silicon oxide layer.