Buried conductive layer supplying digital circuits

An integrated circuit comprising a plurality of layers, the integrated circuit comprising:

• a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers, each of the first pair of vertically stacked transistors are of the same type and are connected in series, wherein the first pair of vertically stacked transistors comprises a common nanowire, wherein the common nanowire comprises channel regions of both transistors of the first pair of vertically stacked transistors;
• a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers, the second pair of transistors being a different type than the first pair of vertically stacked transistors;
• and
• a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors,
• wherein channel regions of the first pair of vertically stacked transistors and the second pair of transistors have an elongated cross section with a longitudinal axis and a transversal axis, wherein the longitudinal axis is longer than the transversal axis, and wherein the longitudinal axis of the elongated cross section is substantially perpendicular to a longitudinal direction of the power supply rail.

A method of forming an integrated circuit comprising a plurality of layers, the method comprising:

• forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers, each of the first pair of vertically stacked transistors are of the same type and are connected in series, wherein the first pair of vertically stacked transistors comprises a common nanowire, wherein the common nanowire comprises channel regions of both transistors of the first pair of vertically stacked transistors;
• forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers, the second pair of transistors being a different type than the first pair of vertically stacked transistors;
• forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors;
• and
• wherein channel regions of the first pair of vertically stacked transistors and the second pair of transistors have a cross section with a longitudinal axis and a transversal axis, wherein the longitudinal axis and the transversal axis are substantially the same length.

A method of forming an integrated circuit comprising a plurality of layers, the method comprising:

• forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers, each of the first pair of vertically stacked transistors are of the same type and are connected in series, wherein the first pair of vertically stacked transistors comprises a common nanowire, wherein the common nanowire comprises channel regions of both transistors of the first pair of vertically stacked transistors;
• forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers, the second pair of transistors being a different type than the first pair of vertically stacked transistors;
• and
• forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors,
• wherein channel regions of the first pair of vertically stacked transistors and the second pair of transistors have an elongated cross section with a longitudinal axis and a transversal axis, wherein the longitudinal axis is longer than the transversal axis, and wherein the longitudinal axis of the elongated cross section is substantially perpendicular to a longitudinal direction of the power supply rail.