Semiconductor memory device and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi
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Abstract
A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.
Claims20
A semiconductor memory device, comprising:
- a semiconductor substrate that includes a trench;
- a gate insulating layer that covers a bottom surface and an inner side surface of the trench;
- a first gate electrode disposed in a lower region of the trench, the first gate electrode comprising a first metal;
- a second gate electrode disposed in the trench and on the first gate electrode;
- and
- a barrier layer disposed between the first gate electrode and the second gate electrode, the barrier layer comprising an oxynitride compound containing the first metal,
- wherein the gate insulating layer comprises a first portion adjacent to the first gate electrode and a second portion adjacent to the second gate electrode, and
- a thickness of the first portion is greater than a thickness of the second portion, when measured in a direction normal to a side surface of the trench.
A semiconductor memory device, comprising:
- a substrate that includes active regions arranged in a first direction and are defined by a device isolation layer;
- a gate line buried in a trench in an upper portion of the substrate, the gate line crossing the active region in a second direction to divide the active region into first and second doped regions, the second direction crossing the first direction;
- a gate insulating layer that separates the trench from the gate line;
- a bit line disposed on the gate line, the bit line extending in a third direction crossing both of the first and second directions;
- and
- a capacitor disposed on the substrate and connected to the second doped region,
- wherein the gate line comprises:
- a first gate electrode disposed in a lower region of the trench, a top surface of the first gate electrode containing oxygen and nitrogen atoms;
- a second gate electrode on the first gate electrode;
- and
- a capping layer on the second gate electrode, and
- wherein a width of the second gate electrode is greater than a width of the first gate electrode.
Dependencies are inferred from the claim text.