Semiconductor devices including transistors comprising a charge trapping material, and related systems and methods

A method of forming a semiconductor device, the method comprising:

• forming an oxide material on sidewalls of trenches in a semiconductive material;
• forming a gate electrode material within the trenches;
• forming another oxide material over at least a portion of the gate electrode material;
• forming a charge trapping material in contact with the oxide material and the another oxide material, the charge trapping material surrounding at least an upper portion of vertically extending sidewalls of the gate electrode, the another oxide material between the vertically extending sidewalls of the gate electrode and the charge trapping material and separating the charge trapping material from the gate electrode;
• forming a source region and a drain region on opposing sides of the trenches to form a transistor, the gate electrode between the source region and the drain region;
• and
• forming a memory storage component in operable communication with the transistor.

A system, comprising:

• at least one processor device operably coupled to at least one input device and at least one output device;
• and
• a semiconductor device operably coupled to the at least one processor device, the semiconductor device comprising at least one memory cell comprising:
• a memory storage element;
• and
• a transistor, the transistor comprising:
• a gate electrode within a base material;
• an oxide material over at least a portion of the gate electrode;
• a charge trapping material over the oxide material;
• another oxide material over sides of the charge trapping material, the charge trapping material directly contacting the another oxide material and the oxide material, the charge trapping material separated from the gate electrode by the oxide material;
• and
• a source region and a drain region on opposing sides of the gate electrode.

A semiconductor device, comprising:

• a memory storage component;
• and
• an array of transistors, at least one transistor of the array of transistors in operable communication with the memory storage component, the at least one transistor comprising:
• a source region, a drain region, and a gate electrode between the source region and the drain region;
• a charge trapping material surrounding at least an upper portion of the gate electrode;
• and
• an oxide material on sides of the charge trapping material, wherein the at least one transistor comprises a greater density of trapped holes than other transistors or the array of transistors.

A system, comprising:

• at least one processor device operably coupled to at least one input device and at least one output device;
• and
• a semiconductor device operably coupled to the at least one processor device, the semiconductor device comprising at least one memory cell comprising:
• a memory storage element;
• and
• a transistor, the transistor comprising:
• a gate electrode within a base material;
• an oxide material over at least a portion of the gate electrode;
• a charge trapping material over the oxide material;
• another oxide material over sides of the charge trapping material, a maximum distance between the gate electrode and the another oxide material between about 5 nm and about 6 nm;
• and
• a source region and a drain region on opposing sides of the gate electrode.