Semiconductor arrangement having continuous spacers and method of manufacturing the same

A method of manufacturing a semiconductor arrangement, comprising operations of:

• forming, on a substrate, a plurality of ridges each extending in a first direction;
• forming, on the substrate, a plurality of sacrificial gate lines each extending continuously in a second direction crossing the first direction to intersect the plurality of ridges;
• forming a spacer on sidewalls of each of the sacrificial gate lines to surround the sacrificial gate line;
• forming first dielectric on the substrate, and planarizing the first dielectric to expose the sacrificial gate lines;
• removing the sacrificial gate lines to expose the underlying ridges;
• filling spaces within the spacers with second dielectric;
• shielding a portion of the second dielectric with a mask and exposing remaining portions of the second dielectric, wherein the mask covers a portion of the second dielectric of a certain dimension in the second direction at at least one of the sacrificial gate lines;
• removing the exposed portions of the second dielectric to expose the underlying ridges;
• and
• forming gate stacks in a space left by the removal of the portions of the second dielectric,
• wherein at the at least one of the sacrificial gate lines, the portion of the second dielectric of the dimension remains, and an interval between gate stacks formed on opposite sides of the remaining portion of the second dielectric in the second direction is defined by the dimension and can therefore be less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

A method of manufacturing a semiconductor arrangement, comprising operations of:

• forming, on a substrate, a plurality of ridges each extending in a first direction;
• forming, on the substrate, a plurality of sacrificial gate lines each extending continuously in a second direction crossing the first direction to intersect the plurality of ridges;
• forming a spacer on sidewalls of each of the sacrificial gate lines to surround the sacrificial gate line;
• forming first dielectric on the substrate, and planarizing the first dielectric to expose the sacrificial gate lines;
• removing the sacrificial gate lines to expose the underlying ridges;
• filling spaces within the spacers with second dielectric;
• shielding a portion of the second dielectric with a first mask and exposing a first portion of the second dielectric;
• removing the exposed first portion of the second dielectric to expose the underlying ridges;
• forming a first gate stack in a space left by the removal of the first portion of the second dielectric;
• shielding a portion of the second dielectric with a second mask and exposing a second portion of the second dielectric, wherein there is an overlay between the first mask and the second mask of a certain dimension in the second direction at at least one of the sacrificial gate lines;
• removing the exposed second portion of the second dielectric to expose the underlying ridges;
• forming a second gate stack in a space left by the removal of the second portion of the second dielectric,
• wherein, at the at least one of the sacrificial gate lines, a portion of the second dielectric corresponding to the overlay of the dimension remains, and the dimension can be less than a Critical Dimension (CD) achievable by photolithography in a process of manufacturing the semiconductor arrangement.