Semiconductor device having a plurality of channel layers and method of manufacturing the same

A semiconductor device comprising:

• a first semiconductor layer including an n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region;
• a buried insulating layer on the first semiconductor layer in the NMOS region;
• a second semiconductor layer on the buried insulating layer;
• a base layer on the first semiconductor layer in the PMOS region;
• a plurality of first channel layers including silicon and spaced apart from one another in a vertical direction on the second semiconductor layer;
• a first gate electrode surrounding the plurality of first channel layers;
• a plurality of second channel layers including silicon and spaced apart from one another in the vertical direction on the base layer;
• and
• a second gate electrode surrounding the plurality of second channel layers,
• wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and
• wherein the base layer has the second crystallographic orientation.