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US 10,833,082 B2Granted
HVMOS reliability evaluation using bulk resistances as indices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Chung Chen, Chi-Feng Huang, Tse-Hua Lu
Life of this patent
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Abstract
A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
Claims20
A structure comprising:
- a semiconductor substrate;
- a plurality of isolation regions in the semiconductor substrate, wherein the plurality of isolation regions are separated from each other;
- a plurality of P-type Metal-Oxide-Semiconductor (PMOS) devices formed at a surface of the semiconductor substrate, wherein the plurality of PMOS devices form an array comprising a plurality of rows and a plurality of columns, wherein each row of the plurality of PMOS devices is encircled by a same one of the plurality of isolation regions;
- and
- an n-type guard ring comprising a plurality of portions, wherein each of the plurality of portions separates two neighboring ones of the plurality of isolation regions from each other.
2 more elements
A structure comprising:
- a semiconductor substrate;
- a heavily doped semiconductor region extending into the semiconductor substrate wherein the heavily doped semiconductor region forms a guard ring;
- a plurality of isolation regions extending into the semiconductor substrate, wherein each of the plurality of isolation regions is separated from other ones of the plurality of isolation regions by the heavily doped semiconductor region;
- a plurality of active regions comprising a plurality of groups of active regions, wherein each group of the plurality of groups of active regions is in one of the plurality of isolation regions, and wherein the plurality of active regions have active-region-to-guard-ring spacings smaller than about 2 μm;
- and
- a plurality of P-type Metal-Oxide-Semiconductor (PMOS) devices formed based on the plurality of active regions.
3 more elements
A structure comprising:
- a semiconductor substrate;
- a heavily doped semiconductor region extending into the semiconductor substrate, wherein the heavily doped semiconductor region is of n-type, and wherein the heavily doped semiconductor region forms a guard ring;
- a plurality of Shallow Trench Isolation (STI) regions extending into the semiconductor substrate and forming a column, wherein each of the plurality of STI regions is separated from other ones of the plurality of STI regions by the heavily doped semiconductor region;
- a plurality of active regions, each encircled by one of the plurality of STI regions, wherein the plurality of active regions have an active-region-to-guard-ring spacing smaller than about 2 μm, and the active-region-to-guard-ring spacing is between a respective one of the plurality of active regions and a nearest portion of the heavily doped semiconductor region;
- and
- a plurality of P-type Metal-Oxide-Semiconductor (PMOS) devices, each comprising one of the plurality of active regions.
3 more elements
Dependencies are inferred from the claim text.