Semiconductor logic element and logic circuitries

A first semiconductor logic element comprising a field effect transistor of a first conductivity type hereinafter referred to as a first FET of the first semiconductor logic element and a field effect transistor of a second conductivity type hereinafter referred to as a second FET of the first semiconductor logic element;

• wherein
• the first semiconductor logic element comprises an internal node of the first semiconductor logic element wherein the internal node of the first semiconductor logic element is at least partly formed with a drain of the first FET of the first semiconductor logic element and a gate of the second FET of the first semiconductor logic element, wherein a gate of the first FET of the first semiconductor logic element is hereinafter referred to as an input of the first semiconductor logic element,
• wherein the input of the first semiconductor logic element is configured to be coupled either to a first input logic potential of the first semiconductor logic element or to a second input logic potential of the first semiconductor logic element,
• wherein a drain of the second FET of the first semiconductor logic element is referred to as an output of the first semiconductor logic element,
• wherein a source of the second FET of the first semiconductor logic element is the source of the first semiconductor logic element,
• wherein the first semiconductor logic element is configured so that when a source of the first FET of the first semiconductor logic element is arranged at a first source potential of the first logic element and when the source of the second FET of the first semiconductor logic element is at a first output logic potential of the first semiconductor logic element and when the input of the first semiconductor logic element is at the first input logic potential of the first semiconductor logic element, a nonconductive channel is established between the source of the first FET of the first semiconductor logic element and the drain of the first FET of the first semiconductor logic element adjusting the internal node of the first semiconductor logic element to a potential causing a channel between the source of the second FET of the first semiconductor logic element and the drain of the second FET of the first semiconductor logic element to be in a nonconductive state thus enabling the output of the first semiconductor logic element to be either at the first output logic potential of the first semiconductor logic element or at a second output logic potential of the first semiconductor logic element, and
• wherein the first semiconductor logic element is further configured so that when the source of the first FET of the first semiconductor logic element is arranged at the first source potential of the first semiconductor logic element and when the source of the second FET of the first semiconductor logic element is at the first output logic potential of the first semiconductor logic element and when the input of the first semiconductor logic element is at the second input logic potential of the first semiconductor logic element, the channel between the source of the first FET of the first semiconductor logic element and the drain of the first FET of the first semiconductor logic element is arranged to be in a nonconductive state enabling the internal node of the first semiconductor logic element to adjust to a potential establishing a conductive channel comprising mobile second conductivity type charge carriers between the source of the second FET of the first semiconductor logic element and the drain of the second FET of the first semiconductor logic element thereby adjusting the output of the first semiconductor logic element to the first output logic potential of the first semiconductor logic element.