Dual transport orientation for stacked vertical transport field-effect transistors

An integrated circuit comprising:

• a stacked vertical transport field-effect transistor structure comprising:
• a substrate;
• at least one vertical fin disposed over a top surface of the substrate;
• a first vertical transport field-effect transistor disposed over the top surface of the substrate surrounding a first portion of the at least one vertical fin;
• an isolation layer disposed over the first vertical transport field-effect transistor surrounding a second portion of the at least one vertical fin;
• and
• a second vertical transport field-effect transistor disposed over a top surface of the isolation layer surrounding a third portion of the at least one vertical fin;
• wherein the first portion of the at least one vertical fin comprises a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first vertical transport field-effect transistor;
• wherein the second portion of the at least one vertical fin comprises an insulator;
• and
• wherein the third portion of the at least one vertical fin comprises a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second vertical transport field-effect transistor;
• a first bottom source/drain region for the first vertical transport field-effect transistor, the first bottom source/drain region comprising a doped region proximate the top surface of the substrate and a doped region of a first portion of the first semiconductor layer proximate the top surface of the substrate;
• a first bottom spacer disposed over the top surface of the substrate and surrounding the first portion of the first semiconductor layer;
• a first gate stack disposed over a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor;
• a first top spacer disposed over a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer;
• and
• a first top source/drain contact for the first vertical transport field-effect transistor disposed over a top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer;
• wherein the third portion of the first semiconductor layer and the fourth portion of the first semiconductor layer are doped to provide a first top source/drain region for the first vertical transport field-effect transistor.

A method of forming a semiconductor structure, comprising:

• forming at least one vertical fin over a top surface of a substrate;
• forming a first vertical transport field-effect transistor over the top surface of the substrate surrounding a first portion of the at least one vertical fin;
• forming an isolation layer over the first vertical transport field-effect transistor surrounding a second portion of the at least one vertical fin;
• and
• forming a second vertical transport field-effect transistor over a top surface of the isolation layer surrounding a third portion of the at least one vertical fin;
• wherein the first portion of the at least one vertical fin comprises a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first vertical transport field-effect transistor;
• wherein the second portion of the at least one vertical fin comprises an insulator;
• and
• wherein the third portion of the at least one vertical fin comprises a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second vertical transport field-effect transistor;
• forming a first bottom source/drain region for the first vertical transport field-effect transistor, the first bottom source/drain region comprising a doped region proximate the top surface of the substrate and a doped region of a first portion of the first semiconductor layer proximate the top surface of the substrate;
• forming a first bottom spacer over the top surface of the substrate and surrounding the first portion of the first semiconductor layer;
• forming a first gate stack over a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor;
• forming a first top spacer over a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer;
• and
• forming a first top source/drain contact for the first vertical transport field-effect transistor over a top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer;
• wherein the third portion of the first semiconductor layer and the fourth portion of the first semiconductor layer are doped to provide a first top source/drain region for the first vertical transport field-effect transistor.

A method of forming a semiconductor structure, comprising:

• forming at least one vertical fin over a top surface of a substrate;
• forming a first vertical transport field-effect transistor over the top surface of the substrate surrounding a first portion of the at least one vertical fin;
• forming an isolation layer over the first vertical transport field-effect transistor surrounding a second portion of the at least one vertical fin;
• and
• forming a second vertical transport field-effect transistor over a top surface of the isolation layer surrounding a third portion of the at least one vertical fin;
• wherein the first portion of the at least one vertical fin comprises a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first vertical transport field-effect transistor;
• wherein the second portion of the at least one vertical fin comprises an insulator;
• and
• wherein the third portion of the at least one vertical fin comprises a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second vertical transport field-effect transistor;
• forming a doped region proximate the top surface of the substrate and in a first portion of the first semiconductor layer, wherein the doped region provides a first bottom source/drain region for the first vertical transport field-effect transistor;
• forming a first bottom spacer over the top surface of the substrate and surrounding the first portion of the first semiconductor layer;
• forming a first gate stack over a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor layer;
• forming a first top spacer over a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer;
• forming a first silicate glass layer over a top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer;
• and
• forming the isolation layer over the first silicate glass layer and surrounding the insulator of the at least one vertical fin;
• wherein the first silicate glass layer comprises one of an n-type dopant material and a p-type dopant material.