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US 10,833,075 B2Granted
Semiconductor integrated circuit device having a standard cell which includes a fin
AssigneeSocionext Inc.
InventorHiroyuki Shimbo
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.
Claims18
A semiconductor integrated circuit device comprising:
- a standard cell having a first fin which extends in a first direction in a first conductivity-type region and a second fin extending in the first direction in a second conductivity-type region which is different from the first conductivity-type region, wherein
- the standard cell comprises:
- a first active transistor including the first fin and a first gate line extending in a second direction perpendicular to the first direction, nodes of the first fin at both sides of the first gate line in the first direction being source and drain of the first active transistor;
- a first dummy transistor including the first fin and a first dummy gate line extending in the second direction, nodes of the first fin at both sides of the first dummy gate line in the first direction being source and drain of the first dummy transistor;
- a second active transistor including the second fin and a second gate line extending in the second direction at a same position as the first gate line in the first direction, nodes of the second fin at both sides of the second gate line in the first direction being source and drain of the second active transistor;
- a third active transistor including the second fin and a third gate line extending in the second direction at a same position as the first dummy gate line in the first direction, nodes of the second fin at both sides of the third gate line in the first direction being source and drain of the third active transistor;
- and
- the first active transistor shares one of its source or drain with the first dummy transistor, and the second active transistor shares one of its source or drain with the third active transistor.
5 more elements
A semiconductor integrated circuit device comprising:
- a standard cell having a first fin which extends in a first direction in a first conductivity-type region and a second fin extending in the first direction in a second conductivity-type region which is different from the first conductivity-type region, wherein
- the standard cell comprises:
- a first active transistor including the first fin and a first gate line extending in a second direction perpendicular to the first direction, nodes of the first fin at both sides of the first gate line in the first direction being source and drain of the first active transistor;
- a first dummy transistor including the first fin and a first dummy gate line extending in the second direction, nodes of the first fin at both sides of the first dummy gate line in the first direction being source and drain of the first dummy transistor;
- a second active transistor including the second fin and a second gate line extending in the second direction at a same position as the first gate line in the first direction, nodes of the second fin at both sides of the second gate line in the first direction being source and drain of the second active transistor;
- a third active transistor including the second fin and a third gate line extending in the second direction at a same position as the first dummy gate line in the first direction, nodes of the second fin at both sides of the third gate line in the first direction being source and drain of the third active transistor;
- a fourth active transistor including the first fin and a fourth gate line extending in the second direction, nodes of the first fin at both sides of the fourth gate line in the first direction being source and drain of the fourth active transistor;
- a fifth active transistor including the second fin and a fifth gate line extending in the second direction at a same position as the fourth gate line in the first direction, nodes of the second fin at both sides of the fifth gate line in the first direction being source and drain of the fifth active transistor;
- and
- the first active transistor shares one of its source or drain with the first dummy transistor, and the first active transistor shares another of its source or drain with the fourth active transistor, and the second active transistor shares one of its source or drain with the third active transistor, and the second active transistor shares another of its source or drain with the fifth active transistor.
7 more elements
Dependencies are inferred from the claim text.