Vertical transistors with different gate lengths

A method for forming a VFET device, comprising the steps of:

• depositing a doped epitaxial layer onto a substrate;
• patterning fins in the doped epitaxial layer and the substrate using fin hardmasks, wherein at least one of the fins comprises a vertical fin channel of a first FET device (FET1) and at least another one of the fins comprises a vertical fin channel of a second FET device (FET2), and wherein the fins extend completely through the doped epitaxial layer and partway through the substrate forming a doped epitaxial portion of the doped epitaxial layer on both the vertical fin channel of the FET1 and the vertical fin channel of the FET2;
• forming a bottom source and drain in the substrate beneath the fins;
• forming bottom spacers on the bottom source and drain;
• forming gates surrounding the vertical fin channel of the FET1 and the vertical fin channel of the FET2;
• forming top spacers on the gates;
• and
• forming top source and drains at the tops of the fins, wherein the step of forming the top source and drains comprises varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the vertical fin channel of the FET2 such that the FET1 has an effective gate length Lgate1 and the FET2 has an effective gate length Lgate2, and wherein Lgate1>Lgate2,
• wherein the method further comprises the steps of:
• depositing an ILD over the fins;
• removing the fin hardmasks to form trenches in the ILD over the fins;
• forming sacrificial spacers along sidewalls of the trenches that cover side portions of the vertical fin channel of the FET1 and the vertical fin channel of the FET2;
• forming a block mask covering the FET1;
• selectively recessing the doped epitaxial portion and the vertical fin channel of the FET2 between the sacrificial spacers such that a sliver of vertical fin channel material remains in the FET2 after the recessing;
• and
• removing the block mask.