Logic gate designs for 3D monolithic direct stacked VTFET
AssigneeInternational Business Machines Corporation
InventorsChen Zhang, Tenko Yamashita, Terence B. Hook
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Abstract
Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device. A method of forming a logic gate device is also provided.
Claims11
A logic gate device, comprising:
- at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2);
- a power rail connected to a power contact of the logic gate device;
- and
- a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device,
- wherein the VTFET1 comprises a first top VTFET (VTFET1A) and a second top VTFET (VTFET1B), and the VTFET2 comprises a first bottom VTFET (VTFET2A) and a second bottom VTFET (VTFET2B), wherein the VTFET1A and the VTFET2A share a first fin, and the VTFET and the VTFET2B share a second fin, and wherein the ground contact is connected to top source and drains of the VTFET2A.
A logic gate device, comprising:
- at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2), wherein the VTFET1 is either a) an NFET if the VTFET2 is a PFET or b) a PFET if the VTFET2 is an NFET;
- a power rail connected to a power contact of the logic gate device;
- and
- a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device,
- wherein the VTFET1 comprises a first top VTFET (VTFET1A) and a second top VTFET (VTFET1B), and the VTFET2 comprises a first bottom VTFET (VTFET2A) and a second bottom VTFET (VTFET2B), wherein the VTFET1A and the VTFET2A share a first fin, and the VTFET1B and the VTFET2B share a second fin, and wherein the ground contact is connected to top source and drains of the VTFET2A.
A logic gate device, comprising:
- at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2);
- a power rail connected to a power contact of the logic gate device;
- and
- a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device, wherein the VTFET1 comprises a first top VTFET (VTFET1A′) and a second top VTFET (VTFET1B′), and the VTFET2 comprises a first bottom VTFET (VTFET2A′) and a second bottom VTFET (VTFET2B′), wherein the VTFET1A′ and the VTFET2A′ share a first fin, and the VTFET1B′ and the VTFET2B′ share a second fin, and wherein the ground contact is connected to bottom source and drains of the VTFET2A′ and the VTFET2B′.
Dependencies are inferred from the claim text.