ESD protection circuit and integrated circuit for broadband circuit

An integrated circuit for a broadband circuit, comprising:

• a high-frequency circuit;
• and
• an ESD protection circuit comprises a signal input end and a signal output end, wherein the high-frequency circuit is electrically coupled with the signal output end, the ESD protection circuit further comprises a silicon-controlled rectifier, an inductor and a trigger unit, the silicon-controlled rectifier is formed by a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material, and a second N-type semiconductor material, which are connected sequentially, the silicon-controlled rectifier comprises a first end, a second end and a third end, the first end is electrically coupled with the first P-type semiconductor material and the signal input end, the second end is electrically coupled with the second N-type semiconductor material, the third end is electrically coupled with the second P-type semiconductor material, one end of the inductor is electrically coupled with the signal input end and the first end, the other end of the inductor is electrically coupled with the signal output end and the high-frequency circuit, one end of the trigger unit is electrically coupled with the signal output end and the high-frequency circuit and the other end of the inductor, and the other end of the trigger unit is electrically coupled with the third end of the silicon-controlled rectifier,
• wherein the ESD protection circuit has a resonance frequency, the high-frequency circuit has an operation frequency, the operation frequency includes an operation frequency range, and the resonance frequency is located within the operation frequency range,
• wherein an inductance value L of the inductor satisfies an equation as follow:
• L
• =
• 2
• ⁢
• Z
• 0
• ⁢
• C
• 1
• +
• 2
• ⁢
• π
• ·
• f
• 0
• ⁢
• Z
• 0
• ⁢
• C
• 2
• wherein, f0 is the resonance frequency, Z0 is a matching impedance of the high-frequency circuit, C1 is a parasitic capacitance value between the first P-type semiconductor material and the second P-type semiconductor material, C3 is a parasitic capacitance value of the trigger unit, and C=C1=C3.