Integrated physically unclonable function device with a set of transistors exhibiting a random distribution of threshold voltages

An integrated circuit comprising:

• a domain comprising a physically unclonable function device, the physically unclonable function device comprising a set of MOS transistors exhibiting a random distribution of respective threshold voltages;
• a first coupling link coupling a group of N first transistors of the set of MOS transistors and a second transistor of the set of MOS transistors via a common node;
• a second coupling link between the common node and an output node of the physically unclonable function device, wherein the first coupling link is configured to:
• generate a principal current and distribute the principal current in the group of N first transistors when the domain is powered and when the first coupling link is in a first state so as to generate for each first transistor of the group of N first transistors a first mean gate source voltage;
• bias a gate of the second transistor by the first mean gate source voltage;
• and
• deliver a reference current to the common node, wherein the reference current is equal to a base current corresponding to i/Nth of the principal current, and wherein the second coupling link is configured to deliver an output signal to the output node, the output signal being dependent on a comparison between the reference current and a current passing through the second transistor, wherein the domain comprises an additional transistor alongside each MOS transistor of the set of MOS transistors, wherein a channel region of the set of MOS transistors comprises dopants of a same type of conductivity as the dopants of a source region and a drain region of the additional transistor.

An integrated circuit, comprising:

• a domain comprising a physically unclonable function device, the physically unclonable function device comprising a set of MOS transistors exhibiting a random distribution of respective threshold voltages;
• a current divider circuit comprising a principal transistor and K secondary transistors;
• N first transistors of the set of MOS transistors coupled to the principal transistor through a common node;
• K second transistors of the set of MOS transistors, each of the K second transistors being coupled to a drain of the K secondary transistors, wherein gates of the N first transistors and the K second transistors are coupled to the common node;
• and
• K comparators, each of the K comparators having a first input coupled to an intermediate node between drains of the K secondary transistors and the K second transistors and a second input coupled to a reference voltage and an output node configured to output a comparison between a first potential at the first input and a second potential at the second input.