3D NAND word line connection structure

A method of manufacturing a memory device, comprising:

• forming a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements;
• forming a first plurality of interlayer connectors, interlayer connectors in the first plurality of interlayer connectors connected to respective linking elements in the first group of linking elements;
• forming a second plurality of interlayer connectors, interlayer connectors in the second plurality of interlayer connectors connected to respective linking elements in the second group of linking elements;
• forming a first layer of patterned conductor lines, patterned conductor lines in the first layer of patterned conductor lines coupled to respective interlayer connectors in the first plurality of interlayer connectors;
• and
• forming a second layer of patterned conductor lines disposed higher than and overlying the first layer of patterned conductor lines, patterned conductor lines in the second layer of patterned conductor lines coupled to respective interlayer connectors in the second plurality of interlayer connectors.