Memory device interconnects and method of manufacture

A method of fabricating an integrated circuit memory device comprising:

• depositing a first dielectric layer on a substrate having a plurality of bit lines and on the plurality of bit lines of the substrate;
• etching a plurality of source line trenches in the first dielectric layer and a plurality of staggered bit line contact openings through the first dielectric layer to a respective one of the plurality of bit lines;
• forming a plurality of source lines in the plurality of source line trenches and a plurality of staggered bit line contacts in the plurality of staggered bit line contact openings from a first metal layer;
• depositing a second dielectric layer on the first dielectric layer;
• depositing an etch stop layer on the first dielectric layer, wherein the etch stop layer also forms or is an anti-reflective layer;
• etching a plurality of source line via windows and a plurality of bit line via windows in the etch stop layer proximate the source lines and the staggered bit line contacts respectively;
• depositing a third dielectric layer on the etch stop layer;
• etching a plurality of trenches in the third dielectric layer that extend to a respective one of the plurality of source line via windows and the plurality of bit line via windows in the etch stop layer, a plurality of the source line via openings through the second dielectric layer to a respective one of the plurality of the source lines, and a plurality of staggered bit line via openings through the second dielectric layer to a respective one of the plurality of staggered bit line contacts;
• and
• forming a plurality of source line metal vias in the plurality of source line via openings, a plurality of staggered bit line metal vias in the plurality of staggered bit line via openings, and a metallization layer in the plurality of trenches in the third dielectric layer from a second metal layer.