Transistor structures having electrically floating metal layers between active metal lines
AssigneeGlobalfoundries Inc.
InventorsChien-Hsin Lee, Haojun Zhang, Mahadeva Iyer Natarajan
Life of this patent
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Abstract
The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.
Claims20
A structure comprising active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines, wherein the electrically floating metal layers are arranged in a cage configuration surrounding the active metal lines on different wiring planes, wherein the active metal lines are source lines and drain lines of an active device.
A structure, comprising:
- a first plurality of active metal lines in a first wiring plane;
- a second plurality of active metal lines in a second wiring plane;
- and
- floating metal layers located between the first plurality of active metal lines and the second plurality of active metal lines to prevent skin effects, wherein the floating metal layers are configured as a cage,
- wherein the first plurality of active metal lines and the second plurality of active metal lines are source lines and drain lines of an active device.
A structure, comprising an upper level of active metal lines;
- a lower level of active metal lines transverse to the upper level;
- and
- a cage of floating metal layers surrounding the active metal lines in the upper level and the lower level and between the upper level and the lower level,
- wherein the cage includes metal vias which surround the active metal lines in the upper level and the lower level in combination with the floating metal layers between the active metal lines in the upper level and the lower level.
Dependencies are inferred from the claim text.