Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorJee Ae Heo
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes an organic interposer, a semiconductor chip, a passivation layer, and an underbump metallurgy (UBM) layer. The organic interposer includes insulating layers and wiring layers disposed on the insulating layers. The semiconductor chip is disposed on one surface of the organic interposer. The passivation layer is disposed on another surface of the organic interposer opposing the one surface on which the semiconductor chip is disposed, and has openings extending to portions of the wiring layer. The UBM layer includes UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other. At least one groove portion is disposed in an outer circumferential surface of the UBM pad.
Claims20
A semiconductor package comprising:
- a substrate including insulating layers and wiring layers;
- a semiconductor chip disposed on an upper surface of the substrate, and connection pads being disposed on a first surface of the semiconductor chip, the first surface of the semiconductor chip being faced with the substrate;
- an encapsulant disposed above the substrate and encapsulating at least a portion of the semiconductor chip;
- a passivation layer disposed on a lower surface of the substrate and covering the insulating layers and a wiring layer of the wiring layers, and an opening being formed in the passivation layer and extending to at least a portion of the wiring layer;
- a pad disposed on the opening and extending out from the passivation layer, thereby having an outer circumferential surface;
- a connection via disposed in the opening and electrically connecting the pad and the wiring layer;
- an electrical connection structure formed on the pad,
- wherein the electrical connection structure covers at least a portion of the outer circumferential surface of the pad.
An interposer comprising:
- an insulating material forming a body of the interposer;
- a plurality of wiring layers disposed in the insulating material of the body;
- a plurality of vias penetrating through the insulating material of the body to interconnect adjacent wiring layers of the plurality of wiring layers;
- a passivation layer disposed on a lower surface of the interposer and covering the insulating material of the body and a wiring layer of the plurality of wiring layers, and an opening being formed in the passivation layer and extending to the wiring layer of the plurality of wiring layers;
- and
- a pad disposed on the opening and extending out from the passivation layer, thereby having an outer circumferential surface;
- a connection via disposed in the opening and electrically connecting the pad and the wiring layer of the plurality of wiring layers;
- and
- an electrical connection structure formed on the pad,
- wherein the electrical connection structure covers at least a portion of the outer circumferential surface of the pad.
Dependencies are inferred from the claim text.