Stress modulation of nFET and pFET fin structures

A monolithic structure comprising:

• an nFET region and a pFET region, each of the nFET and pFET regions including:
• a plurality of semiconductor fins, the semiconductor fins including channel regions, each of the channel regions having a top channel boundary and a bottom channel boundary,
• a plurality of gate structures extending across the plurality of semiconductor fins,
• source/drain regions on opposing sides of each of the plurality of gate structures and operatively associated with the channel regions,
• a fin cut region extending across the plurality of semiconductor fins, and
• a pair of opposing semiconductor fin end portions separated by the fin cut region;
• a dielectric tensile stressor layer on the monolithic structure, the dielectric tensile stressor layer including a first portion extending into the fin cut region of the nFET region;
• and
• a metal compressive stressor layer within the fin cut region in the pFET region;
• wherein the first portion of the dielectric tensile stressor layer induces substantially uniaxial tensile stress in the direction of electrical current flow on the semiconductor fins in the nFET region and the metal compressive stressor layer induces substantially uniaxial compressive stress in the direction of electrical current flow on the semiconductor fins in the pFET region.