US 10,832,972 B2Granted

Semiconductor arrangement having continuous spacers and method of manufacturing the same

AssigneeInstitute of Microelectronics, Chinese Academy of Sciences

InventorsHuilong Zhu, Huicai Zhong, Yanbo Zhang

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Abstract

A semiconductor arrangement includes: a substrate; a plurality of fins formed on the substrate and extending in a first direction; a plurality of gate stacks formed on the substrate and extending in a second direction crossing the first direction and dummy gates composed of dielectric and extending in the second direction, wherein each of the gate stacks intersects at least one of the fins; and spacers formed on sidewalls of the gate stacks and sidewalls of the dummy gates, wherein spacers of at least a first one and a second one among the gate stacks and the dummy gates which are aligned in the second direction extend integrally, and at least some of the fins have ends abutting the dummy gates and substantially aligned with inner walls of corresponding ones of the spacers.

Claims16

Dependent claims

A semiconductor arrangement, comprising:

a substrate;
a plurality of fins formed on the substrate and extending in a first direction;
a plurality of gate stacks formed on the substrate and extending in a second direction crossing the first direction and dummy gates composed of dielectric and extending in the second direction, wherein each of the gate stacks intersects at least one of the fins;
spacers formed on sidewalls of the gate stacks and sidewalls of the dummy gates,
wherein spacers of at least a first one and a second one of the gate stacks which are aligned in the second direction or spacers of at least one of the gate stacks and at least one of the dummy gates which are aligned in the second direction extend integrally,
wherein at least some of the fins have ends abutting the dummy gates and substantially aligned with inner walls of corresponding ones of the spacers, and
wherein at least one of the dummy gates has a seam therein which extends in substantially the second direction and extends vertically from a top surface of the dummy gate downward;
and
wherein dielectric is disposed between the first gate stack and the second gate stack, wherein the dielectric is disposed in a space between the spacers of the first gate stack and the second gate stack which extend integrally, and wherein the dielectric has a seam therein which extends in substantially the second direction and extends vertically from a top surface of the dummy gate downward.

6 more elements

A method of manufacturing a semiconductor arrangement, comprising operations of:

forming, on a substrate, a plurality of ridges each extending continuously in a first direction;
forming, on the substrate, a plurality of sacrificial gate lines each extending continuously in a second direction crossing the first direction to intersect the plurality of ridges;
forming a spacer on sidewalls of each of the sacrificial gate lines to surround the sacrificial gate line;
forming first dielectric on the substrate, and planarizing the first dielectric to expose the sacrificial gate lines;
removing the sacrificial gate lines to expose the underlying ridges;
selectively etching portions of the exposed ridges;
filling spaces within the spacers with second dielectric;
removing portions of the second dielectric to expose the underlying ridges;
and
forming gate stacks in a space left by the removal of the portions of the second dielectric,
wherein forming the gate stacks comprises forming different first and second gate stacks in a space surrounded by one same spacer, wherein the first gate stack and the second gate stack have the second dielectric left therebetween.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/327,973Filed 21 Dec 2016
Priority: CN 2016 1 102546115 Nov 2016
Published: US 2019/0189523 A120 Jun 2019
Granted: 10 Nov 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/795
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in lateral device isolation regions, e.g. STI
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…