Formation of an air gap spacer using sacrificial spacer layer

A method for manufacturing a semiconductor device, comprising:

• forming a plurality of gate structures on a semiconductor fin;
• forming a plurality of cap layers on the plurality of gate structures;
• forming a plurality of source/drain regions on sides of the plurality of gate structures;
• conformally depositing a sacrificial spacer layer on the plurality of source/drain regions and on the plurality of gate structures, wherein the sacrificial spacer layer comprises germanium oxide;
• removing a first portion of the sacrificial spacer layer, wherein the removal exposes portions of the plurality of source/drain regions;
• wherein removing the first portion of the sacrificial spacer layer leaves remaining portions of the sacrificial spacer layer on parts of top surfaces of the plurality of source/drain regions;
• wherein the remaining portions of the sacrificial spacer layer have a height less than a height of the plurality of cap layers;
• forming a plurality of source/drain contacts on the plurality of source/drain regions and on the remaining portions of the sacrificial spacer layer, wherein the remaining portions of the sacrificial spacer layer are positioned between the plurality of source/drain contacts and adjacent ones of the plurality of gate structures, and wherein portions of the plurality of source/drain contacts cover the remaining portions of the sacrificial spacer layer;
• planarizing the plurality of source/drain contacts;
• etching the plurality of source/drain contacts following the planarizing to a height less than the height of the plurality of cap layers to expose the remaining portions of the sacrificial spacer layer;
• removing the remaining portions of the sacrificial spacer layer to form a plurality of spaces between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures;
• and
• non-conformally depositing a dielectric material in the plurality of spaces and on the plurality of source/drain contacts, wherein the dielectric material comprises a plurality of air gaps.

A method for manufacturing a semiconductor device, comprising:

• forming a plurality of gate structures on a semiconductor layer;
• forming a plurality of cap layers on the plurality of gate structures;
• forming a plurality of source/drain regions adjacent the plurality of gate structures;
• depositing a sacrificial spacer layer on the plurality of source/drain regions;
• removing a first portion of the sacrificial spacer layer to expose portions of the plurality of source/drain regions;
• wherein removing the first portion of the sacrificial spacer layer leaves remaining portions of the sacrificial spacer layer on parts of top surfaces of the plurality of source/drain regions;
• wherein the remaining portions of the sacrificial spacer layer have a height less than a height of the plurality of cap layers;
• forming a plurality of source/drain contacts on the plurality of source/drain regions and on the remaining portions of the sacrificial spacer layer, wherein the remaining portions of the sacrificial spacer layer are positioned between the plurality of source/drain contacts and adjacent ones of the plurality of gate structures, and wherein portions of the plurality of source/drain contacts cover the remaining portions of the sacrificial spacer layer;
• planarizing the plurality of source/drain contacts;
• etching the plurality of source/drain contacts following the planarizing to a height less than the height of the plurality of cap layers to expose the remaining portions of the sacrificial spacer layer;
• removing the remaining portions of the sacrificial spacer layer to form a plurality of spaces between the plurality of source/drain contacts and the adjacent ones of the plurality of gate structures, wherein the removal of the remaining portions of the sacrificial spacer layer is performed using a water-based etch;
• and
• non-conformally depositing a dielectric material in the plurality of spaces and on the plurality of source/drain contacts, wherein the dielectric material comprises a plurality of air gaps.