Quadruple gate dielectric for gate-all-around transistors

A method for constructing devices with different gate dielectric thicknesses, the method comprising:

• forming a first nanosheet stack for a first device, a second nanosheet stack for a second device, a third nanosheet stack for a third device, and a fourth nanosheet stack for a fourth device;
• removing sacrificial layers from the first, second, third, and fourth nanosheet stacks;
• forming an interfacial dielectric around alternate semiconductor layers of the first, second, third, and fourth devices;
• depositing a first sacrificial capping layer;
• selectively removing the first sacrificial capping layer from the first and third devices;
• depositing a second sacrificial capping layer and an oxygen blocking layer;
• selectively removing the oxygen blocking layer from the third and fourth devices;
• and
• performing an anneal to create different gate dielectric thicknesses for each of the first, second, third, and fourth devices.