Method and structure for forming transistors with high aspect ratio gate without patterning collapse

Abstract

A method for fabricating transistors comprises forming a fin above a semiconductor substrate; forming an isolation region with a dielectric material, the top surface of the isolation dielectric below the top of fin surface; depositing a dummy gate layer above the isolation region and surrounding the fin, a dummy gate hardmask layer on top of the dummy gate layer, a first hardmask material on top of the dummy gate hardmask layer above the fin and a second hardmask material on top of the dummy gate hardmask layer above the isolation region, the first hardmask material having a greater lateral etch than the second hardmask material; applying a gate patterning mask spaced equidistantly apart on top of the first and second hardmask materials; and etching the transistor to simultaneously form narrow active gates above and surrounding the fin and wide dummy gates above the isolation region.

Dependencies are inferred from the claim text.