US 10,832,952 B2Granted

Selective recessing to form a fully aligned via

AssigneeTessera, Inc.

InventorsBenjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert

Life of this patent

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Abstract

A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Claims20

Dependent claims

A method comprising:

forming a plurality of metal lines in a first dielectric layer;
recessing in a recess region a first portion of a first metal line such that a top surface of the first portion of the first metal line is below a top surface of the first dielectric layer;
and
forming a tri-layer mask pattern on a low temperature oxide layer, wherein the tri-layer mask pattern includes a photoresist layer selectively patterned to form an opening such that the photoresist is on top of second portions of the plurality of metal lines and is not on top of the first portion of the plurality of metal lines, the opening having a width that overlaps every metal line among the plurality of metal lines;
and
recessing in a recess region a first portion of a separate metal line such that a top surface of the first portion of the separate metal line is below a top surface of the first dielectric layer,
wherein a non-recess region comprises second portions of the first metal line that are outside the recess region.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/014,025Filed 21 Jun 2018 · division
Priority: 5 Aug 2016
Published: US 2018/0040510 A11 Nov 2018
Granted: 10 Nov 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/062
Of conductive parts of the interconnections: by smoothing of conductive parts, e.g. by planarisation
H10W 20/0693
By forming self-aligned vias or self-aligned contact plugs: by forming self-aligned vias

Family

Application15/229,470Parent of this division · filed 5 Aug 2016
US 2018/0315654 A1Pre-grant publication · published 1 Nov 2018
US 10,276,436 B2Parent of this division
US 2018/0040510 A1Published application
US 10,832,952 B2This patent

From the US filing history. Foreign family members aren’t listed.