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US 10,832,951 B2Granted
Interconnect wires including relatively low resistivity cores
AssigneeIntel Corporation
InventorsHui Jae Yoo, Tejaswi K. Indukuri, Ramanan V. Chebiam, James S. Clarke
Life of this patent
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Abstract
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.
Claims11
A method of forming a wire in a dielectric layer, comprising:
- forming a first opening in a dielectric layer;
- depositing a conformal coating of a first layer of a jacket material on said dielectric layer and forming a second opening in said first opening, wherein said jacket material exhibits a first resistivity p1;
- depositing a core material on said conformal coating, wherein said core material exhibits a second resistivity p2 and p2 is less than p1, and wherein said core material partially fills said second opening;
- and
- depositing a second layer of said jacket material over said core material and said first layer of said jacket material, filling said second opening and forming a wire, wherein said core material is in a volume surrounded by said jacket material, the core material completely filling the volume surrounded by said jacket material.
2 more elements
An integrated circuit, comprising:
- a dielectric layer;
- a plurality of openings defined in said dielectric layer;
- and
- a plurality of wires, wherein each wire is positioned within one of said openings and each wire includes a core material in a volume completely surrounded by a jacket material in a vertical cross-sectional view, the core material completely filling the volume surrounded by said jacket material, wherein said jacket material is within the one of said openings, and wherein said jacket material exhibits a first resistivity p1 and said core material exhibits a second resistivity p2 and p2 is less than p1.
1 more element
An integrated circuit, comprising:
- a dielectric layer having an uppermost surface;
- a plurality of openings defined in said dielectric layer;
- and
- a plurality of wires, wherein each wire is positioned within one of said openings and each wire includes a core material in a volume completely surrounded by a jacket material in a vertical cross-sectional view, the core material completely filling the volume surrounded by said jacket material, wherein said jacket material has an uppermost surface co-planar with the uppermost surface of the dielectric layer, and wherein said jacket material exhibits a first resistivity pI and said core material exhibits a second resistivity p2 and p2 is less than p1.
1 more element
Dependencies are inferred from the claim text.