Fully aligned via formation without metal recessing
AssigneeInternational Business Machines Corporation
InventorsChanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
Life of this patent
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Abstract
A method is presented for forming fully aligned vias without recessing a plurality of conductive lines. The method includes forming the plurality of conductive lines within an interlayer dielectric (ILD), growing first dielectric regions in direct contact with the plurality of conductive lines, forming a capping layer over the first dielectric regions, depositing an ultra-low-k (ULK) layer over and in direct contact with the capping layer, forming a via over a conductive line of the plurality of conductive lines, and removing an exposed portion of the capping layer and an exposed first dielectric region in direct contact with the conductive line to reveal the conductive line.
Claims20
A method for forming fully aligned vias without recessing a plurality of conductive lines, the method comprising:
- forming the plurality of conductive lines within an interlayer dielectric (ILD);
- growing first dielectric regions, defining discontinuous segments, in direct contact with the plurality of conductive lines;
- forming a capping layer over the first dielectric regions;
- depositing an ultra-low-k (ULK) layer over and in direct contact with the capping layer;
- forming a via over a conductive line of the plurality of conductive lines;
- and
- removing an exposed portion of the capping layer and an exposed first dielectric region in direct contact with the conductive line to reveal the conductive line.
A method for forming fully aligned vias without recessing a plurality of copper (Cu) lines, the method comprising:
- depositing aluminum nitride (AlN) on the plurality of Cu lines;
- depositing aluminum oxynitride (AlNO) on inter-layer dielectric (ILD) surfaces of a Cu damascene line structure;
- removing the AlON selective to the AlN to form AlN capped Cu lines;
- coating and planarizing a first ultra-low-k (ULK) ILD layer;
- depositing a capping layer and a second ULK ILD layer;
- patterning a via in the second ULK ILD layer;
- etching through the capping layer;
- and
- selectively removing an exposed AlN resulting in a via bottom opening fully aligned and confined on the Cu line below.
A semiconductor structure for forming fully aligned vias without recessing a plurality of conductive lines, the semiconductor structure comprising:
- the plurality of conductive lines disposed within an interlayer dielectric (ILD);
- first dielectric regions, defining discontinuous segments, disposed in direct contact with one or more of the plurality of conductive lines;
- a capping layer in direct contact with the first dielectric regions;
- an ultra-low-k (ULK) layer disposed over and in direct contact with the capping layer;
- a via disposed over a conductive line of the plurality of conductive lines, the via formed without recessing the conductive line;
- and
- a conductive material disposed within the via.
Dependencies are inferred from the claim text.