Recessed interconnet line having a low-oxygen cap for facilitating a robust planarization process and protecting the interconnect line from downstream etch operations

A method of forming an interconnect structure in a metallization layer of a multi-layered integrated circuit, the method comprising:

• forming a dielectric region having a dielectric region top surface, wherein the dielectric top surface is substantially planar;
• forming a first interconnect structure in the dielectric region, wherein the first interconnect structure comprises a first liner and a first interconnect body-, wherein the first interconnect body comprises a first interconnect body top surface, wherein the first interconnect body top surface comprises an unintended non-planar region;
• and
• applying a reinforced planarization process comprising:
• recessing the first interconnect body top surface to a level that is below the dielectric region top surface and the unintended non-planar region, thereby removing the unintended non-planar region and forming a second interconnect body having a second interconnect body top surface, wherein the second interconnect body top surface is substantially planar;
• forming a protective cap on the second interconnect body top surface, wherein the protective cap has a protective cap top surface, wherein the protective cap top surface is substantially planar;
• depositing a sacrificial dielectric region over the protective cap;
• and
• applying a selective planarization process that planarizes and recesses the dielectric region top surface, a top surface of the first liner, and the sacrificial dielectric region faster than it planarizes and recesses the protective cap;
• wherein the protective cap acts as a planarization stop layer to the selective planarization process when the selective planarization process reaches the protective cap top surface.

A metallization layer of a multi-layered integrated circuit, the metallization layer comprising:

• a dielectric region having a dielectric region top surface, wherein the dielectric top surface is substantially planar, wherein the dielectric region comprises a dielectric region planarization selectivity characteristic comprising a first selectivity to a selective planarization process used to planarize the dielectric top surface;
• an interconnect structure in the dielectric region, wherein the interconnect structure comprises an interconnect structure top surface, wherein the interconnect structure top surface is substantially planar;
• and
• a protective cap and planarization-stop (PCPS) region on the interconnect structure top surface, wherein the PCPS region has a PCPS region top surface, wherein the PCPS region top surface is substantially planar, wherein the PCPS region comprises a PCPS region planarization selectivity characteristic comprising a second selectivity to the selective planarization process used to planarize the dielectric top surface;
• wherein the first selectivity is greater than the second selectivity;
• and
• wherein the dielectric region top surface is substantially planar with the protective cap top surface.