Interconnect structure having reduced resistance variation and method of forming same
AssigneeGlobalfoundries Inc.
InventorsNicholas V. LiCausi, Chanro Park, Ruilong Xie, Andre P. Labonte
Life of this patent
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Abstract
An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.
Claims18
An interconnect structure of an integrated circuit, the interconnect structure comprising:
- at least two metal lines laterally spaced from one another in a dielectric layer, the at least two metal lines having a top surface below a top surface of the dielectric layer;
- a hardmask layer on an upper portion of sidewalls of the at least two metal lines, the hardmask layer having a portion extending between the at least two metal lines, the extending portion being below the top surface of the metal lines;
- at least one fully aligned via on the top surface of a given metal line of the at least two metal lines;
- and
- an etch stop layer having a first portion directly on the dielectric layer and a second portion directly on any portion of the at least two metal lines not having the at least one fully aligned via thereon, and surrounding the at least one fully aligned via.
An interconnect structure of an integrated circuit, the interconnect structure comprising:
- a dielectric layer;
- a pair of metal lines laterally spaced from one another within the dielectric layer, wherein each of the pair of metal lines includes a top surface below a top surface of the dielectric layer, and wherein the top surface of each of the pair of metal lines is coplanar and flat;
- a hardmask layer on an upper portion of a sidewall of each of the pair of metal lines, the hardmask layer having a portion extending between the pair of metal lines and below the top surface of the metal lines;
- at least one fully aligned via on the top surface of one of the pair of metal lines, wherein the at least one fully aligned via is wider than the one of the pair of metal lines;
- and
- an etch stop layer having a first portion directly on the dielectric layer and a second portion directly on any portion of the at least two metal lines not having the at least one fully aligned via thereon, and surrounding the at least one fully aligned via.
An interconnect structure of an integrated circuit, the interconnect structure comprising:
- a dielectric layer;
- a pair of metal lines laterally spaced from one another within the dielectric layer, wherein each of the pair of metal lines includes a top surface below a top surface of the dielectric layer, and wherein the top surface of each of the pair of metal lines is coplanar and flat;
- a hardmask layer on an upper portion of a sidewall of each of the pair of metal lines, the hardmask layer having a portion extending between the pair of metal lines and below the top surface of the metal lines;
- at least one fully aligned via on the top surface of one of the pair of metal lines, wherein the at least one fully aligned via is wider than the one of the pair of metal lines;
- an inter-layer dielectric (ILD) over the dielectric layer, over any portion of the pair of metal lines not having a via thereon, and surrounding the at least one fully aligned via;
- and
- an etch stop layer between the ILD and the dielectric layer and between the ILD and the any portion of the pair of metal lines not having a via thereon.
Dependencies are inferred from the claim text.